projet-vlsi/alu.vhdl

library ieee;
use ieee.math_real.all;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;

entity ALU is
	port (
		op1	: IN	std_logic_vector(31 downto 0);
		op2	: IN	std_logic_vector(31 downto 0);
		cin	: IN	std_logic;
		cmd	: IN	std_logic_vector(1 downto 0);
		res	: out	std_logic_vector(31 downto 0);
		cout	: out	std_logic;
		z	: out	std_logic;
		n	: out	std_logic;
		v	: out	std_logic;
		vdd	: IN	bit;
		vss	: IN	bit
	);
end ALU;

--------------------------------------------------------------------------------

architecture ALU_bhvr of ALU is
	signal cout_temp, add_cout : std_logic;
	signal res_temp, add  : std_logic_vector(31 downto 0);

begin

	adder_0: entity work.adder32_ent
		port map(
			cin	=> cin,
			i0	=> op1,
 	 		i1	=> op2,
 	 		q	=> add,
 	 		cout	=> add_cout
 	 	);

	process(op1, op2, cin, cmd, vss , vdd, add, add_cout)
	begin
		case cmd is
			when "00" =>
 	 	-- report "ADD";
		res_temp <= add;
		cout_temp <= add_cout;

			when "01" =>
		-- report "AND";
		res_temp <= op1 and op2 ;
		cout_temp <= '0';
			when "10" =>
		-- report "OR ";
		res_temp <= op1 or  op2;
		cout_temp <= '0';
			when "11" =>
		-- report "XOR";
		res_temp <= op1 xor op2 ;
		cout_temp <= '0';
			when others =>
		report "[ERROR] SWITCH CASE UNREACHABLE (Alu::cmd not initialised ?)";
		end case;
	end process;

	process(res_temp, cout_temp)
		begin

		if (res_temp="00000000000000000000000000000000")
			 	then z <= '1';
			 	else z <= '0';
		end if;

		n <= res_temp(31);
		v <= res_temp(31) xor cout_temp;
		cout <= cout_temp;
 		res <= res_temp;
	end process;

end ALU_bhvr;