projet-vlsi/alu.vhdl

library ieee;
use ieee.math_real.all;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;

entity Alu is
    port ( op1  : in  Std_Logic_Vector(31 downto 0);
         op2  : in  Std_Logic_Vector(31 downto 0);
         cin  : in  Std_Logic;
         cmd  : in  Std_Logic_Vector(1 downto 0);
         res  : out Std_Logic_Vector(31 downto 0);
         cout : out Std_Logic;
         z    : out Std_Logic;
         n    : out Std_Logic;
         v    : out Std_Logic;
         vdd  : in  bit;
         vss  : in  bit );
end Alu;

--------------------------------------------------------------------------------

architecture Alu_bhvr of Alu is
    signal cout_temp, add_cout : std_logic;
    signal res_temp, add  : Std_Logic_Vector(31 downto 0);

    begin
    
    adder_0: entity work.adder_32bit_ent
                    PORT MAP(
                    	cin => cin,  	
                    	 i0 => op1,
 	 	         i1 => op2,
 	 	          q => add,
 	 	       cout => add_cout
 	 	       	    );

    process(op1, op2, cin, cmd, vss , vdd, add, add_cout)
    begin
        case cmd is 
            when "00" => 
 	 	report "ADD";
		res_temp <= add;
		cout_temp <= add_cout;
 	 	
            when "01" => 
		report "AND";
		res_temp <= op1 and op2 ;
		cout_temp <= '0';
            when "10" => 
		report "OR ";
		res_temp <= op1 or  op2;
		cout_temp <= '0';
            when "11" => 
		report "XOR";
		res_temp <= op1 xor op2 ;
		cout_temp <= '0';
            when others => 
		report "ERROR";
        end case;
    end process;

    process(res_temp, cout_temp)
    	begin
		
        if (res_temp="00000000000000000000000000000000") 
             	then z <= '1';
             	else z <= '0';
        end if;

        n <= res_temp(31);
        v <= res_temp(31) XOR cout_temp;
		cout <= cout_temp;
 		res <= res_temp;
    end process;

end Alu_bhvr;