78 lines
1.8 KiB
VHDL
78 lines
1.8 KiB
VHDL
library ieee;
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use ieee.math_real.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_1164.all;
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entity Alu is
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port ( op1 : in Std_Logic_Vector(31 downto 0);
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op2 : in Std_Logic_Vector(31 downto 0);
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cin : in Std_Logic;
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cmd : in Std_Logic_Vector(1 downto 0);
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res : out Std_Logic_Vector(31 downto 0);
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cout : out Std_Logic;
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z : out Std_Logic;
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n : out Std_Logic;
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v : out Std_Logic;
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vdd : in bit;
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vss : in bit );
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end Alu;
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--------------------------------------------------------------------------------
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architecture Alu_bhvr of Alu is
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signal cout_temp, add_cout : std_logic;
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signal res_temp, add : Std_Logic_Vector(31 downto 0);
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begin
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adder_0: entity work.adder_32bit_ent
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PORT MAP(
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cin => cin,
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i0 => op1,
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i1 => op2,
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q => add,
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cout => add_cout
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);
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process(op1, op2, cin, cmd, vss , vdd, add, add_cout)
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begin
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case cmd is
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when "00" =>
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report "ADD";
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res_temp <= add;
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cout_temp <= add_cout;
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when "01" =>
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report "AND";
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res_temp <= op1 and op2 ;
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cout_temp <= '0';
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when "10" =>
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report "OR ";
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res_temp <= op1 or op2;
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cout_temp <= '0';
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when "11" =>
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report "XOR";
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res_temp <= op1 xor op2 ;
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cout_temp <= '0';
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when others =>
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report "ERROR";
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end case;
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end process;
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process(res_temp, cout_temp)
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begin
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if (res_temp="00000000000000000000000000000000")
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then z <= '1';
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else z <= '0';
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end if;
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n <= res_temp(31);
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v <= res_temp(31) XOR cout_temp;
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cout <= cout_temp;
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res <= res_temp;
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end process;
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end Alu_bhvr;
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