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projet-vlsi
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Adrien Bourmault 2021-10-26 19:06:02 +02:00
parent 9363214539
commit 92bbd9f141
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library ieee;
use ieee.std_logic_1164.all;
entity C3P is
port (A, B : in std_logic;
C : in std_logic;
S1 : out std_logic;
S2 : out std_logic);
end C3P;
architecture dataflow of C3P is
signal X : std_logic;
begin
PROCESS (A, B, C)
VARIABLE X : std_logic;
BEGIN
X := A AND B;
S1 <= C XOR X;
END PROCESS;
PROCESS (C, A)
VARIABLE CetA : std_logic_vector(1 DOWNTO 0);
BEGIN
CetA := C & A;
CASE CetA IS
WHEN "00" => S2 <= '1';
WHEN OTHERS => S2 <= '0';
END CASE;
END PROCESS;
end dataflow;

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library ieee;
use ieee.std_logic_1164.all;
entity C3P is
port (A, B : in std_logic;
C : in std_logic;
S1 : out std_logic;
S2 : out std_logic);
end C3P;
architecture dataflow of C3P is
signal X : std_logic;
begin
PROCESS (A, B, C)
VARIABLE X : std_logic;
BEGIN
X := A AND B;
S1 <= C XOR X;
END PROCESS;
PROCESS (C, A)
VARIABLE CetA : std_logic_vector(1 DOWNTO 0);
BEGIN
CetA := C & A;
CASE CetA IS
WHEN "00" => S2 <= '1';
WHEN OTHERS => S2 <= '0';
END CASE;
END PROCESS;
end dataflow;

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library ieee;
use ieee.std_logic_1164.all;
entity C3P is
port (A, B : in std_logic;
C : in std_logic;
S1 : out std_logic;
S2 : out std_logic);
end C3P;
architecture dataflow of C3P is
signal X : std_logic;
begin
X <= A AND B;
S1 <= C XOR X;
S2 <= C NOR A;
end dataflow;

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library ieee;
use ieee.std_logic_1164.all;
--library work;
--use work.bidon.all;
-- A testbench has no ports.
entity c3p_tb is
end c3p_tb;
architecture Structurel of c3p_tb is
-- Declaration un composant
component C3P
port (A, B : in std_logic;
C : in std_logic;
S1 : out std_logic;
S2 : out std_logic);
end component;
signal A, B, C, S1, S2 : std_logic;
begin
C3P_0: C3P
port map ( A => A,
B => B,
C => C,
S1 => S1,
S2 => S2);
process
function nat_to_std (v: in natural) return std_logic is
variable res : std_logic;
begin
if v = 1 then
res := '1';
else
res := '0';
end if;
return res;
end function nat_to_std;
variable vs1 : std_logic;
variable vs2 : std_logic;
begin
La : for va in 0 to 1 loop
Lb : for vb in 0 to 1 loop
Lc : for vc in 0 to 1 loop
A <= nat_to_std(va);
B <= nat_to_std(vb);
C <= nat_to_std(vc);
vs1 := nat_to_std(vc) xor ( nat_to_std(va) and nat_to_std(vb));
vs2 := nat_to_std(vc) nor nat_to_std(va);
wait for 1 ns;
assert vs1 = S1 report "Erreur sur S1" severity error;
assert vs2 = S2 report "Erreur sur S2" severity error;
end loop Lc;
end loop Lb;
end loop La;
assert false report "end of test" severity note;
-- Wait forever; this will finish the simulation.
wait;
end process;
end Structurel;

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GHDL = ghdl
all : sim
adder1bit.o : adder1bit.vhdl
${GHDL} -a -v adder1bit.vhdl
adder_32bit.o : adder_32bit.vhdl adder1bit.o
${GHDL} -a -v adder_32bit.vhdl
adder_32bit_tb.o : adder_32bit_tb.vhdl adder_32bit.o
${GHDL} -a -v adder_32bit_tb.vhdl
adder_32bit_tb : adder_32bit_tb.o
${GHDL} -e -v adder_32bit_tb
alu.o : alu.vhdl adder_32bit.o
${GHDL} -a -v alu.vhdl
alu_tb.o : alu_tb.vhdl alu.o
${GHDL} -a -v alu_tb.vhdl
alu_tb : alu.o alu_tb.o
${GHDL} -e -v alu_tb
shifter.o : shifter.vhdl
${GHDL} -a -v shifter.vhdl
shifter_tb.o : shitfter_tb.vhdl shifter.o
${GHDL} -a -v shifter_tb.vhdl
shifter_tb : shitfter_tb.o
${GHDL} -e -v shifter_tb
sim_adder_32bit : adder_32bit_tb
${GHDL} -r adder_32bit_tb --vcd=adder_32bit.vcd
sim : alu_tb
${GHDL} -r alu_tb --vcd=alu.vcd
clean :
-rm *.o work-obj93.cf *_tb *.vcd

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library ieee;
use ieee.math_real.all;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
--use work.adder1bit.all;
-----------------------------------------------------------------
-- ADDER 4 BIT
-----------------------------------------------------------------
ENTITY adder_4bit_ent IS
PORT (
i0, i1 : IN std_logic_vector(3 downto 0);
q : OUT std_logic_vector(3 downto 0)
);
END ENTITY;
-----------------------------------------------------------------
ARCHITECTURE adder_4bit OF adder_4bit_ent IS
--COMPONENT adder1bit IS
--PORT (
-- i0, i1, cin : IN std_logic;
-- q, cout : OUT std_logic
--);
--END COMPONENT;
SIGNAL co : std_logic_vector(3 downto 0);
BEGIN
adder0 : entity work.adder1bit
PORT MAP (
i0 => i0(0),
i1 => i1(0),
cin => '0',
q => q(0),
cout => co(0)
);
loop_3: for i in 1 to 3 generate
adderN : entity work.adder1bit
PORT MAP (
i0 => i0(i),
i1 => i1(i),
cin => co(i-1),
q => q(i),
cout => co(i)
);
END GENERATE loop_3;
END adder_4bit;

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library ieee;
use ieee.math_real.all;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
-- ADDER 1 BIT
----------------------------------------------------------------
ENTITY adder1bit IS
PORT (
i0, i1, cin : IN std_logic;
q, cout : OUT std_logic
);
END ENTITY;
-----------------------------------------------------------------
ARCHITECTURE full_adder_1bit OF adder1bit IS
BEGIN
q <= i0 XOR i1 XOR cin;
cout <= (i0 and i1) or (i0 and cin) or (i1 and cin);
END full_adder_1bit;

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library ieee;
use ieee.math_real.all;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
-----------------------------------------------------------------
-- ADDER 32 BIT
-----------------------------------------------------------------
ENTITY adder_32bit_ent IS
PORT (
cin : IN std_logic;
i0, i1 : IN std_logic_vector(31 downto 0);
q : OUT std_logic_vector(31 downto 0);
cout : OUT std_logic
);
END ENTITY;
-----------------------------------------------------------------
ARCHITECTURE adder_32bit OF adder_32bit_ent IS
SIGNAL co : std_logic_vector(31 downto 0);
BEGIN
adder0 : entity work.adder1bit
PORT MAP (
i0 => i0(0),
i1 => i1(0),
cin => cin,
q => q(0),
cout => co(0)
);
loop_29: for i in 1 to 30 generate
adder_32bitN : entity work.adder1bit
PORT MAP (
i0 => i0(i),
i1 => i1(i),
cin => co(i-1),
q => q(i),
cout => co(i)
);
END GENERATE loop_29;
adder31 : entity work.adder1bit
PORT MAP (
i0 => i0(31),
i1 => i1(31),
cin => co(30),
q => q(31),
cout => cout
);
END adder_32bit;

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LIBRARY ieee;
use ieee.math_real.all;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
---
ENTITY adder_32bit_tb IS
END adder_32bit_tb;
---
ARCHITECTURE Structurel OF adder_32bit_tb is
COMPONENT adder
PORT (
cin : IN std_logic;
i0, i1 : IN std_logic_vector(31 downto 0);
q : OUT std_logic_vector(31 downto 0);
cout : OUT std_logic
);
END COMPONENT;
SIGNAL cout, cin : std_logic;
SIGNAL i0, i1, q_32 : std_logic_vector(31 downto 0);
signal vadd : std_logic_vector(31 downto 0);
impure function rand_int(min_val, max_val : integer) return integer is
variable r : real;
variable seed1, seed2 : integer := 998;
begin
uniform(seed1, seed2, r);
return integer(
round(r * real(max_val - min_val + 1) + real(min_val) - 0.5));
end function;
BEGIN
adder_0: entity work.adder_32bit_ent
PORT MAP(
cin => cin,
i0 => i0,
i1 => i1,
q => q_32,
cout => cout
);
process
variable rva, rvb : integer;
begin
cin <= '0';
loop_i0: for va in 0 to 15 loop
loop_i1: for vb in 0 to 15 loop
rva := rand_int(-200, 200);
rvb := rand_int(-200, 200);
i0 <= std_logic_vector(to_unsigned(va, 32));
i1 <= std_logic_vector(to_unsigned(vb, 32));
vadd <= std_logic_vector(to_unsigned(va+vb, 32));
wait for 2 fs;
REPORT "i0 : " & integer'image(to_integer(unsigned(i0)))
& " + i1 : "
& integer'image(to_integer(unsigned(i1)))
& " = "
& integer'image(to_integer(unsigned(q_32)))
& " ( vadd = "
& integer'image(to_integer(unsigned(vadd)))
& " ) ";
ASSERT vadd = q_32 REPORT "ERROR not equal !" SEVERITY ERROR;
end loop loop_i1;
end loop loop_i0;
WAIT;
end process;
END Structurel;

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY adder_tb IS
END adder_tb;
ARCHITECTURE Structurel OF adder_tb is
COMPONENT adder
PORT (
i0, i1 : IN std_logic_vector(3 downto 0);
q : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
SIGNAL i0, i1, q : std_logic_vector(3 downto 0);
signal vadd : std_logic_vector(3 downto 0);
BEGIN
adder_0: entity work.adder_4bit_ent
PORT MAP( i0 => i0,
i1 => i1,
q => q);
process
begin
loop_i0: for va in 0 to 15 loop
loop_i1: for vb in 0 to 15 loop
i0 <= std_logic_vector(to_unsigned(va, 4));
i1 <= std_logic_vector(to_unsigned(vb, 4));
vadd <= std_logic_vector(to_unsigned(va+vb, 4));
REPORT "i0 : " & integer'image(to_integer(unsigned(i0)))
& " + i1 : "
& integer'image(to_integer(unsigned(i1)))
& " = "
& integer'image(to_integer(unsigned(q)));
ASSERT vadd = q REPORT "ERROR not equal !" SEVERITY ERROR;
wait for 2 fs;
end loop loop_i1;
end loop loop_i0;
WAIT;
end process;
END Structurel;

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library ieee;
use ieee.math_real.all;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity Alu is
port ( op1 : in Std_Logic_Vector(31 downto 0);
op2 : in Std_Logic_Vector(31 downto 0);
cin : in Std_Logic;
cmd : in Std_Logic_Vector(1 downto 0);
res : out Std_Logic_Vector(31 downto 0);
cout : out Std_Logic;
z : out Std_Logic;
n : out Std_Logic;
v : out Std_Logic;
vdd : in bit;
vss : in bit );
end Alu;
--------------------------------------------------------------------------------
architecture Alu_bhvr of Alu is
signal cout_temp, add_cout : std_logic;
signal res_temp, add : Std_Logic_Vector(31 downto 0);
begin
adder_0: entity work.adder_32bit_ent
PORT MAP(
cin => cin,
i0 => op1,
i1 => op2,
q => add,
cout => add_cout
);
process(op1, op2, cin, cmd, vss , vdd, add, add_cout)
begin
case cmd is
when "00" =>
report "ADD";
res_temp <= add;
cout_temp <= add_cout;
when "01" =>
report "AND";
res_temp <= op1 and op2 ;
cout_temp <= '0';
when "10" =>
report "OR ";
res_temp <= op1 or op2;
cout_temp <= '0';
when "11" =>
report "XOR";
res_temp <= op1 xor op2 ;
cout_temp <= '0';
when others =>
report "ERROR";
end case;
end process;
process(res_temp, cout_temp)
begin
if (res_temp="00000000000000000000000000000000")
then z <= '1';
else z <= '0';
end if;
n <= res_temp(31);
v <= res_temp(31) XOR cout_temp;
cout <= cout_temp;
res <= res_temp;
end process;
end Alu_bhvr;

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library ieee;
use ieee.math_real.all;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity alu_tb is
end alu_tb;
ARCHITECTURE Structurel OF alu_tb is
signal op1 : Std_Logic_Vector(31 downto 0) := std_logic_vector(to_unsigned(32654, 32));
signal op2 : Std_Logic_Vector(31 downto 0) := std_logic_vector(to_unsigned(65877, 32));
signal cin : Std_Logic := '0';
signal cmd : Std_Logic_Vector(1 downto 0) := "00";
signal res : Std_Logic_Vector(31 downto 0) := (others => '0');
signal cout : Std_Logic;
signal z : Std_Logic;
signal n : Std_Logic;
signal v : Std_Logic;
signal vdd : bit := '1';
signal vss : bit := '0';
begin
alu_ins: entity work.alu
PORT MAP(
op1 => op1,
op2 => op2,
cin => cin,
cmd => cmd,
res => res,
cout => cout,
z => z,
n => n,
v => v,
vdd => vdd,
vss => vss
);
process
begin
wait for 5 fs;
cmd <= "00";
wait for 5 fs;
report "op1 = " & integer'image(to_integer(unsigned(op1)));
report "op2 = " & integer'image(to_integer(unsigned(op2)));
report "res = " & integer'image(to_integer(unsigned(res)));
assert z/='1'report "z";
assert n/='1'report "n";
assert v/='1'report "v";
wait for 5 fs;
cmd <= "01";
wait for 5 fs;
report "op1 = " & integer'image(to_integer(unsigned(op1)));
report "op2 = " & integer'image(to_integer(unsigned(op2)));
report "res = " & integer'image(to_integer(unsigned(res)));
assert z/='1'report "z";
assert n/='1'report "n";
assert v/='1'report "v";
wait for 5 fs;
cmd <= "10";
wait for 5 fs;
report "op1 = " & integer'image(to_integer(unsigned(op1)));
report "op2 = " & integer'image(to_integer(unsigned(op2)));
report "res = " & integer'image(to_integer(unsigned(res)));
assert z/='1'report "z";
assert n/='1'report "n";
assert v/='1'report "v";
wait for 5 fs;
cmd <= "11";
wait for 5 fs;
report "op1 = " & integer'image(to_integer(unsigned(op1)));
report "op2 = " & integer'image(to_integer(unsigned(op2)));
report "res = " & integer'image(to_integer(unsigned(res)));
assert z/='1'report "z";
assert n/='1'report "n";
assert v/='1'report "v";
wait for 5 fs;
cmd <= "00";
wait for 5 fs;
report "op1 = " & integer'image(to_integer(unsigned(op1)));
report "op2 = " & integer'image(to_integer(unsigned(op2)));
report "res = " & integer'image(to_integer(unsigned(res)));
assert z/='1'report "z";
assert n/='1'report "n";
assert v/='1'report "v";
wait for 5 fs;
cmd <= "00";
wait for 5 fs;
report "op1 = " & integer'image(to_integer(unsigned(op1)));
report "op2 = " & integer'image(to_integer(unsigned(op2)));
report "res = " & integer'image(to_integer(unsigned(res)));
assert z/='1'report "z";
assert n/='1'report "n";
assert v/='1'report "v";
wait for 50 fs;
WAIT;
end process;
END Structurel;

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