34 lines
520 B
VHDL
34 lines
520 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity C3P is
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port (A, B : in std_logic;
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C : in std_logic;
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S1 : out std_logic;
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S2 : out std_logic);
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end C3P;
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architecture dataflow of C3P is
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signal X : std_logic;
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begin
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PROCESS (A, B, C)
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VARIABLE X : std_logic;
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BEGIN
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X := A AND B;
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S1 <= C XOR X;
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END PROCESS;
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PROCESS (C, A)
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VARIABLE CetA : std_logic_vector(1 DOWNTO 0);
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BEGIN
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CetA := C & A;
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CASE CetA IS
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WHEN "00" => S2 <= '1';
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WHEN OTHERS => S2 <= '0';
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END CASE;
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END PROCESS;
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end dataflow;
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