68 lines
1.3 KiB
VHDL
68 lines
1.3 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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--library work;
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--use work.bidon.all;
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-- A testbench has no ports.
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entity c3p_tb is
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end c3p_tb;
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architecture Structurel of c3p_tb is
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-- Declaration un composant
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component C3P
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port (A, B : in std_logic;
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C : in std_logic;
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S1 : out std_logic;
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S2 : out std_logic);
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end component;
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signal A, B, C, S1, S2 : std_logic;
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begin
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C3P_0: C3P
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port map ( A => A,
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B => B,
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C => C,
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S1 => S1,
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S2 => S2);
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process
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function nat_to_std (v: in natural) return std_logic is
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variable res : std_logic;
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begin
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if v = 1 then
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res := '1';
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else
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res := '0';
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end if;
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return res;
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end function nat_to_std;
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variable vs1 : std_logic;
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variable vs2 : std_logic;
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begin
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La : for va in 0 to 1 loop
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Lb : for vb in 0 to 1 loop
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Lc : for vc in 0 to 1 loop
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A <= nat_to_std(va);
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B <= nat_to_std(vb);
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C <= nat_to_std(vc);
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vs1 := nat_to_std(vc) xor ( nat_to_std(va) and nat_to_std(vb));
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vs2 := nat_to_std(vc) nor nat_to_std(va);
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wait for 1 ns;
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assert vs1 = S1 report "Erreur sur S1" severity error;
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assert vs2 = S2 report "Erreur sur S2" severity error;
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end loop Lc;
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end loop Lb;
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end loop La;
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assert false report "end of test" severity note;
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-- Wait forever; this will finish the simulation.
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wait;
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end process;
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end Structurel;
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