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projet-vlsi
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Merge branch 'tests' into 'main' 

Makefile and syntax cleaned

See merge request neox/projet-vlsi!2
This commit is contained in:
Adrien Bourmault 2021-10-27 09:20:58 +00:00
parent 63289494cb 4b012f6a53
commit 41b9dd9986
12 changed files with 313 additions and 409 deletions
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3
.gitignore vendored Normal file
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*.vcd
*.cf
*.o

45
Makefile
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GHDL = ghdl
all : sim
all : sim_alu #sim_shifter
adder1bit.o : adder1bit.vhdl
${GHDL} -a -v adder1bit.vhdl
%.o : %.vhdl
${GHDL} -a -g -v $^
adder_32bit.o : adder_32bit.vhdl adder1bit.o
${GHDL} -a -v adder_32bit.vhdl
adder32_tb : adder1.o adder32.o adder32_tb.o
${GHDL} -e -v adder32_tb
adder_32bit_tb.o : adder_32bit_tb.vhdl adder_32bit.o
${GHDL} -a -v adder_32bit_tb.vhdl
adder_32bit_tb : adder_32bit_tb.o
${GHDL} -e -v adder_32bit_tb
alu.o : alu.vhdl adder_32bit.o
${GHDL} -a -v alu.vhdl
alu_tb.o : alu_tb.vhdl alu.o
${GHDL} -a -v alu_tb.vhdl
alu_tb : alu.o alu_tb.o
${GHDL} -e -v alu_tb
shifter.o : shifter.vhdl
${GHDL} -a -v shifter.vhdl
shifter_tb.o : shitfter_tb.vhdl shifter.o
${GHDL} -a -v shifter_tb.vhdl
shifter_tb : shitfter_tb.o
shifter_tb : shitfter.o shitfter_tb.o
${GHDL} -e -v shifter_tb
sim_adder_32bit : adder_32bit_tb
${GHDL} -r adder_32bit_tb --vcd=adder_32bit.vcd
alu_tb : adder1.o adder32.o alu.o alu_tb.o
${GHDL} -e -v alu_tb
sim : alu_tb
sim_adder32 : adder32_tb
${GHDL} -r adder32_tb --vcd=adder32.vcd
sim_alu : alu_tb
${GHDL} -r alu_tb --vcd=alu.vcd
sim_shifter : shifter_tb
${GHDL} -r shifter_tb --vcd=shifter.vcd
clean :
-rm *.o work-obj93.cf *_tb *.vcd

48
adder.vhdl
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library ieee;
use ieee.math_real.all;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
--use work.adder1bit.all;
-----------------------------------------------------------------
-- ADDER 4 BIT
-----------------------------------------------------------------
ENTITY adder_4bit_ent IS
PORT (
i0, i1 : IN std_logic_vector(3 downto 0);
q : OUT std_logic_vector(3 downto 0)
);
END ENTITY;
-----------------------------------------------------------------
ARCHITECTURE adder_4bit OF adder_4bit_ent IS
--COMPONENT adder1bit IS
--PORT (
-- i0, i1, cin : IN std_logic;
-- q, cout : OUT std_logic
--);
--END COMPONENT;
SIGNAL co : std_logic_vector(3 downto 0);
BEGIN
adder0 : entity work.adder1bit
PORT MAP (
i0 => i0(0),
i1 => i1(0),
cin => '0',
q => q(0),
cout => co(0)
);
loop_3: for i in 1 to 3 generate
adderN : entity work.adder1bit
PORT MAP (
i0 => i0(i),
i1 => i1(i),
cin => co(i-1),
q => q(i),
cout => co(i)
);
END GENERATE loop_3;
END adder_4bit;

23
adder1.vhdl Normal file
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library ieee;
use ieee.math_real.all;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
-- ADDER 1 BIT
----------------------------------------------------------------
entity adder1_ent is
port (
i0, i1, cin : IN std_logic;
q, cout : OUT std_logic
);
end entity;
architecture adder1 of adder1_ent is
begin
q <= i0 xor i1 xor cin;
cout <= (i0 and i1) or (i0 and cin) or (i1 and cin);
end adder1;

20
adder1bit.vhdl
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library ieee;
use ieee.math_real.all;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
-- ADDER 1 BIT
----------------------------------------------------------------
ENTITY adder1bit IS
PORT (
i0, i1, cin : IN std_logic;
q, cout : OUT std_logic
);
END ENTITY;
-----------------------------------------------------------------
ARCHITECTURE full_adder_1bit OF adder1bit IS
BEGIN
q <= i0 XOR i1 XOR cin;
cout <= (i0 and i1) or (i0 and cin) or (i1 and cin);
END full_adder_1bit;

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adder32.vhdl Normal file
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library ieee;
use ieee.math_real.all;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
-----------------------------------------------------------------
-- adder 32 bit
-----------------------------------------------------------------
entity adder32_ent is
port (
cin : IN std_logic;
i0, i1 : IN std_logic_vector(31 downto 0);
q : OUT std_logic_vector(31 downto 0);
cout : OUT std_logic
);
end entity;
architecture adder32 of adder32_ent is
signal co : std_logic_vector(31 downto 0);
begin
adder32_0 : entity work.adder1_ent
port map (
i0 => i0(0),
i1 => i1(0),
cin => cin,
q => q(0),
cout => co(0)
);
loop_29: for i in 1 to 30 generate
adder32_n : entity work.adder1_ent
port map (
i0 => i0(i),
i1 => i1(i),
cin => co(i-1),
q => q(i),
cout => co(i)
);
end generate loop_29;
adder32_31 : entity work.adder1_ent
port map (
i0 => i0(31),
i1 => i1(31),
cin => co(30),
q => q(31),
cout => cout
);
end adder32;

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adder32_tb.vhdl Normal file
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library ieee;
use ieee.math_real.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
---
entity adder32_tb is
end adder32_tb;
---
architecture Structurel of adder32_tb is
-- component adder
-- port (
-- cin : IN std_logic;
-- i0, i1 : IN std_logic_vector(31 downto 0);
-- q : OUT std_logic_vector(31 downto 0);
-- cout : OUT std_logic
-- );
-- end component;
signal cout, cin : std_logic;
signal i0, i1, q_32 : std_logic_vector(31 downto 0);
signal vadd : std_logic_vector(31 downto 0);
impure function rand_int(min_val, max_val : integer) return integer is
variable r : real;
variable seed1, seed2 : integer := 998;
begin
uniform(seed1, seed2, r);
return integer(
round(r * real(max_val - min_val + 1) + real(min_val) - 0.5));
end function;
begin
adder_0: entity work.adder32_ent
port map(
cin => cin,
i0 => i0,
i1 => i1,
q => q_32,
cout => cout
);
process
variable rva, rvb : integer;
begin
cin <= '0';
loop_i0: for va in 0 to 15 loop
loop_i1: for vb in 0 to 15 loop
rva := rand_int(-200, 200);
rvb := rand_int(-200, 200);
i0 <= std_logic_vector(to_unsigned(va, 32));
i1 <= std_logic_vector(to_unsigned(vb, 32));
vadd <= std_logic_vector(to_unsigned(va+vb, 32));
wait for 2 fs;
report "i0 : " & integer'image(to_integer(unsigned(i0)))
& " + i1 : "
& integer'image(to_integer(unsigned(i1)))
& " = "
& integer'image(to_integer(unsigned(q_32)))
& " ( vadd = "
& integer'image(to_integer(unsigned(vadd)))
& " ) ";
assert vadd = q_32 report "ERROR not equal !" severity error;
end loop loop_i1;
end loop loop_i0;
wait;
end process;
end Structurel;

53
adder_32bit.vhdl
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@ -1,53 +0,0 @@
library ieee;
use ieee.math_real.all;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
-----------------------------------------------------------------
-- ADDER 32 BIT
-----------------------------------------------------------------
ENTITY adder_32bit_ent IS
PORT (
cin : IN std_logic;
i0, i1 : IN std_logic_vector(31 downto 0);
q : OUT std_logic_vector(31 downto 0);
cout : OUT std_logic
);
END ENTITY;
-----------------------------------------------------------------
ARCHITECTURE adder_32bit OF adder_32bit_ent IS
SIGNAL co : std_logic_vector(31 downto 0);
BEGIN
adder0 : entity work.adder1bit
PORT MAP (
i0 => i0(0),
i1 => i1(0),
cin => cin,
q => q(0),
cout => co(0)
);
loop_29: for i in 1 to 30 generate
adder_32bitN : entity work.adder1bit
PORT MAP (
i0 => i0(i),
i1 => i1(i),
cin => co(i-1),
q => q(i),
cout => co(i)
);
END GENERATE loop_29;
adder31 : entity work.adder1bit
PORT MAP (
i0 => i0(31),
i1 => i1(31),
cin => co(30),
q => q(31),
cout => cout
);
END adder_32bit;

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adder_32bit_tb.vhdl
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@ -1,77 +0,0 @@
LIBRARY ieee;
use ieee.math_real.all;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
---
ENTITY adder_32bit_tb IS
END adder_32bit_tb;
---
ARCHITECTURE Structurel OF adder_32bit_tb is
COMPONENT adder
PORT (
cin : IN std_logic;
i0, i1 : IN std_logic_vector(31 downto 0);
q : OUT std_logic_vector(31 downto 0);
cout : OUT std_logic
);
END COMPONENT;
SIGNAL cout, cin : std_logic;
SIGNAL i0, i1, q_32 : std_logic_vector(31 downto 0);
signal vadd : std_logic_vector(31 downto 0);
impure function rand_int(min_val, max_val : integer) return integer is
variable r : real;
variable seed1, seed2 : integer := 998;
begin
uniform(seed1, seed2, r);
return integer(
round(r * real(max_val - min_val + 1) + real(min_val) - 0.5));
end function;
BEGIN
adder_0: entity work.adder_32bit_ent
PORT MAP(
cin => cin,
i0 => i0,
i1 => i1,
q => q_32,
cout => cout
);
process
variable rva, rvb : integer;
begin
cin <= '0';
loop_i0: for va in 0 to 15 loop
loop_i1: for vb in 0 to 15 loop
rva := rand_int(-200, 200);
rvb := rand_int(-200, 200);
i0 <= std_logic_vector(to_unsigned(va, 32));
i1 <= std_logic_vector(to_unsigned(vb, 32));
vadd <= std_logic_vector(to_unsigned(va+vb, 32));
wait for 2 fs;
REPORT "i0 : " & integer'image(to_integer(unsigned(i0)))
& " + i1 : "
& integer'image(to_integer(unsigned(i1)))
& " = "
& integer'image(to_integer(unsigned(q_32)))
& " ( vadd = "
& integer'image(to_integer(unsigned(vadd)))
& " ) ";
ASSERT vadd = q_32 REPORT "ERROR not equal !" SEVERITY ERROR;
end loop loop_i1;
end loop loop_i0;
WAIT;
end process;
END Structurel;

45
adder_tb.vhdl
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@ -1,45 +0,0 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY adder_tb IS
END adder_tb;
ARCHITECTURE Structurel OF adder_tb is
COMPONENT adder
PORT (
i0, i1 : IN std_logic_vector(3 downto 0);
q : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
SIGNAL i0, i1, q : std_logic_vector(3 downto 0);
signal vadd : std_logic_vector(3 downto 0);
BEGIN
adder_0: entity work.adder_4bit_ent
PORT MAP( i0 => i0,
i1 => i1,
q => q);
process
begin
loop_i0: for va in 0 to 15 loop
loop_i1: for vb in 0 to 15 loop
i0 <= std_logic_vector(to_unsigned(va, 4));
i1 <= std_logic_vector(to_unsigned(vb, 4));
vadd <= std_logic_vector(to_unsigned(va+vb, 4));
REPORT "i0 : " & integer'image(to_integer(unsigned(i0)))
& " + i1 : "
& integer'image(to_integer(unsigned(i1)))
& " = "
& integer'image(to_integer(unsigned(q)));
ASSERT vadd = q REPORT "ERROR not equal !" SEVERITY ERROR;
wait for 2 fs;
end loop loop_i1;
end loop loop_i0;
WAIT;
end process;
END Structurel;

40
alu.vhdl
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@ -3,30 +3,32 @@ use ieee.math_real.all;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity Alu is
port ( op1 : in Std_Logic_Vector(31 downto 0);
op2 : in Std_Logic_Vector(31 downto 0);
cin : in Std_Logic;
cmd : in Std_Logic_Vector(1 downto 0);
res : out Std_Logic_Vector(31 downto 0);
cout : out Std_Logic;
z : out Std_Logic;
n : out Std_Logic;
v : out Std_Logic;
vdd : in bit;
vss : in bit );
end Alu;
entity ALU is
port (
op1 : IN std_logic_vector(31 downto 0);
op2 : IN std_logic_vector(31 downto 0);
cin : IN std_logic;
cmd : IN std_logic_vector(1 downto 0);
res : out std_logic_vector(31 downto 0);
cout : out std_logic;
z : out std_logic;
n : out std_logic;
v : out std_logic;
vdd : IN bit;
vss : IN bit
);
end ALU;
--------------------------------------------------------------------------------
architecture Alu_bhvr of Alu is
architecture ALU_bhvr of ALU is
signal cout_temp, add_cout : std_logic;
signal res_temp, add : Std_Logic_Vector(31 downto 0);
signal res_temp, add : std_logic_vector(31 downto 0);
begin
adder_0: entity work.adder_32bit_ent
PORT MAP(
adder_0: entity work.adder32_ent
port map(
cin => cin,
i0 => op1,
i1 => op2,
@ -68,10 +70,10 @@ architecture Alu_bhvr of Alu is
end if;
n <= res_temp(31);
v <= res_temp(31) XOR cout_temp;
v <= res_temp(31) xor cout_temp;
cout <= cout_temp;
res <= res_temp;
end process;
end Alu_bhvr;
end ALU_bhvr;

34
alu_tb.vhdl
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@ -3,27 +3,28 @@ use ieee.math_real.all;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity alu_tb is
end alu_tb;
entity ALU_tb is
end ALU_tb;
ARCHITECTURE Structurel OF alu_tb is
signal op1 : Std_Logic_Vector(31 downto 0) := std_logic_vector(to_unsigned(32654, 32));
signal op2 : Std_Logic_Vector(31 downto 0) := std_logic_vector(to_unsigned(65877, 32));
signal cin : Std_Logic := '0';
signal cmd : Std_Logic_Vector(1 downto 0) := "00";
signal res : Std_Logic_Vector(31 downto 0) := (others => '0');
signal cout : Std_Logic;
signal z : Std_Logic;
signal n : Std_Logic;
signal v : Std_Logic;
architecture Structurel of ALU_tb is
signal op1 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(32654, 32));
signal op2 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(65877, 32));
signal cin : std_logic := '0';
signal cmd : std_logic_vector(1 downto 0) := "00";
signal res : std_logic_vector(31 downto 0) := (others => '0');
signal cout : std_logic;
signal z : std_logic;
signal n : std_logic;
signal v : std_logic;
signal vdd : bit := '1';
signal vss : bit := '0';
begin
alu_ins: entity work.alu
PORT MAP(
ALU_ins: entity work.ALU
port map(
op1 => op1,
op2 => op2,
cin => cin,
@ -36,6 +37,7 @@ PORT MAP(
vdd => vdd,
vss => vss
);
process
begin
@ -105,7 +107,7 @@ assert v/='1'report "v";
wait for 50 fs;
WAIT;
wait;
end process;
END Structurel;
end Structurel;