From 4b012f6a537446d9cdaef432a4c8d6b49f6924b1 Mon Sep 17 00:00:00 2001 From: Adrien Bourmault Date: Wed, 27 Oct 2021 09:20:58 +0000 Subject: [PATCH] Makefile and syntax cleaned --- .gitignore | 3 + Makefile | 45 ++++------- adder.vhdl | 48 ------------ adder1.vhdl | 23 ++++++ adder1bit.vhdl | 20 ----- adder32.vhdl | 54 ++++++++++++++ adder32_tb.vhdl | 78 +++++++++++++++++++ adder_32bit.vhdl | 53 ------------- adder_32bit_tb.vhdl | 77 ------------------- adder_tb.vhdl | 45 ----------- alu.vhdl | 98 ++++++++++++------------ alu_tb.vhdl | 178 ++++++++++++++++++++++---------------------- 12 files changed, 313 insertions(+), 409 deletions(-) create mode 100644 .gitignore delete mode 100644 adder.vhdl create mode 100644 adder1.vhdl delete mode 100644 adder1bit.vhdl create mode 100644 adder32.vhdl create mode 100644 adder32_tb.vhdl delete mode 100644 adder_32bit.vhdl delete mode 100644 adder_32bit_tb.vhdl delete mode 100644 adder_tb.vhdl diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..7259c57 --- /dev/null +++ b/.gitignore @@ -0,0 +1,3 @@ +*.vcd +*.cf +*.o diff --git a/Makefile b/Makefile index df8bc5a..a9c4f94 100644 --- a/Makefile +++ b/Makefile @@ -1,41 +1,26 @@ GHDL = ghdl -all : sim +all : sim_alu #sim_shifter -adder1bit.o : adder1bit.vhdl - ${GHDL} -a -v adder1bit.vhdl +%.o : %.vhdl + ${GHDL} -a -g -v $^ -adder_32bit.o : adder_32bit.vhdl adder1bit.o - ${GHDL} -a -v adder_32bit.vhdl +adder32_tb : adder1.o adder32.o adder32_tb.o + ${GHDL} -e -v adder32_tb -adder_32bit_tb.o : adder_32bit_tb.vhdl adder_32bit.o - ${GHDL} -a -v adder_32bit_tb.vhdl - -adder_32bit_tb : adder_32bit_tb.o - ${GHDL} -e -v adder_32bit_tb - -alu.o : alu.vhdl adder_32bit.o - ${GHDL} -a -v alu.vhdl - -alu_tb.o : alu_tb.vhdl alu.o - ${GHDL} -a -v alu_tb.vhdl - -alu_tb : alu.o alu_tb.o - ${GHDL} -e -v alu_tb - -shifter.o : shifter.vhdl - ${GHDL} -a -v shifter.vhdl - -shifter_tb.o : shitfter_tb.vhdl shifter.o - ${GHDL} -a -v shifter_tb.vhdl - -shifter_tb : shitfter_tb.o +shifter_tb : shitfter.o shitfter_tb.o ${GHDL} -e -v shifter_tb -sim_adder_32bit : adder_32bit_tb - ${GHDL} -r adder_32bit_tb --vcd=adder_32bit.vcd +alu_tb : adder1.o adder32.o alu.o alu_tb.o + ${GHDL} -e -v alu_tb -sim : alu_tb +sim_adder32 : adder32_tb + ${GHDL} -r adder32_tb --vcd=adder32.vcd + +sim_alu : alu_tb ${GHDL} -r alu_tb --vcd=alu.vcd +sim_shifter : shifter_tb + ${GHDL} -r shifter_tb --vcd=shifter.vcd + clean : -rm *.o work-obj93.cf *_tb *.vcd diff --git a/adder.vhdl b/adder.vhdl deleted file mode 100644 index 31d24d3..0000000 --- a/adder.vhdl +++ /dev/null @@ -1,48 +0,0 @@ -library ieee; -use ieee.math_real.all; -use ieee.numeric_std.all; -use ieee.std_logic_1164.all; ---use work.adder1bit.all; - ------------------------------------------------------------------ --- ADDER 4 BIT ------------------------------------------------------------------ -ENTITY adder_4bit_ent IS -PORT ( - i0, i1 : IN std_logic_vector(3 downto 0); - q : OUT std_logic_vector(3 downto 0) -); -END ENTITY; ------------------------------------------------------------------ -ARCHITECTURE adder_4bit OF adder_4bit_ent IS - ---COMPONENT adder1bit IS ---PORT ( --- i0, i1, cin : IN std_logic; --- q, cout : OUT std_logic ---); ---END COMPONENT; - -SIGNAL co : std_logic_vector(3 downto 0); - -BEGIN -adder0 : entity work.adder1bit -PORT MAP ( - i0 => i0(0), - i1 => i1(0), - cin => '0', - q => q(0), - cout => co(0) -); -loop_3: for i in 1 to 3 generate -adderN : entity work.adder1bit -PORT MAP ( - i0 => i0(i), - i1 => i1(i), - cin => co(i-1), - q => q(i), - cout => co(i) -); -END GENERATE loop_3; -END adder_4bit; - diff --git a/adder1.vhdl b/adder1.vhdl new file mode 100644 index 0000000..6375bb5 --- /dev/null +++ b/adder1.vhdl @@ -0,0 +1,23 @@ +library ieee; +use ieee.math_real.all; +use ieee.numeric_std.all; +use ieee.std_logic_1164.all; + + +-- ADDER 1 BIT +---------------------------------------------------------------- + +entity adder1_ent is + port ( + i0, i1, cin : IN std_logic; + q, cout : OUT std_logic + ); +end entity; + + +architecture adder1 of adder1_ent is + +begin + q <= i0 xor i1 xor cin; + cout <= (i0 and i1) or (i0 and cin) or (i1 and cin); +end adder1; diff --git a/adder1bit.vhdl b/adder1bit.vhdl deleted file mode 100644 index 64d9d14..0000000 --- a/adder1bit.vhdl +++ /dev/null @@ -1,20 +0,0 @@ -library ieee; -use ieee.math_real.all; -use ieee.numeric_std.all; -use ieee.std_logic_1164.all; - - --- ADDER 1 BIT ----------------------------------------------------------------- -ENTITY adder1bit IS -PORT ( - i0, i1, cin : IN std_logic; - q, cout : OUT std_logic -); -END ENTITY; ------------------------------------------------------------------ -ARCHITECTURE full_adder_1bit OF adder1bit IS -BEGIN - q <= i0 XOR i1 XOR cin; - cout <= (i0 and i1) or (i0 and cin) or (i1 and cin); -END full_adder_1bit; diff --git a/adder32.vhdl b/adder32.vhdl new file mode 100644 index 0000000..f43ffc1 --- /dev/null +++ b/adder32.vhdl @@ -0,0 +1,54 @@ +library ieee; +use ieee.math_real.all; +use ieee.numeric_std.all; +use ieee.std_logic_1164.all; + +----------------------------------------------------------------- +-- adder 32 bit +----------------------------------------------------------------- + +entity adder32_ent is + port ( + cin : IN std_logic; + i0, i1 : IN std_logic_vector(31 downto 0); + q : OUT std_logic_vector(31 downto 0); + cout : OUT std_logic + ); +end entity; + + +architecture adder32 of adder32_ent is + + signal co : std_logic_vector(31 downto 0); + +begin + adder32_0 : entity work.adder1_ent + port map ( + i0 => i0(0), + i1 => i1(0), + cin => cin, + q => q(0), + cout => co(0) + ); + + loop_29: for i in 1 to 30 generate + + adder32_n : entity work.adder1_ent + port map ( + i0 => i0(i), + i1 => i1(i), + cin => co(i-1), + q => q(i), + cout => co(i) + ); + end generate loop_29; + + adder32_31 : entity work.adder1_ent + port map ( + i0 => i0(31), + i1 => i1(31), + cin => co(30), + q => q(31), + cout => cout + ); +end adder32; diff --git a/adder32_tb.vhdl b/adder32_tb.vhdl new file mode 100644 index 0000000..ec0d5a4 --- /dev/null +++ b/adder32_tb.vhdl @@ -0,0 +1,78 @@ +library ieee; +use ieee.math_real.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +--- + +entity adder32_tb is +end adder32_tb; + +--- + +architecture Structurel of adder32_tb is + + -- component adder + -- port ( + -- cin : IN std_logic; + -- i0, i1 : IN std_logic_vector(31 downto 0); + -- q : OUT std_logic_vector(31 downto 0); + -- cout : OUT std_logic + -- ); + -- end component; + + signal cout, cin : std_logic; + signal i0, i1, q_32 : std_logic_vector(31 downto 0); + signal vadd : std_logic_vector(31 downto 0); + + impure function rand_int(min_val, max_val : integer) return integer is + variable r : real; + variable seed1, seed2 : integer := 998; + begin + uniform(seed1, seed2, r); + return integer( + round(r * real(max_val - min_val + 1) + real(min_val) - 0.5)); + end function; + +begin + + adder_0: entity work.adder32_ent + port map( + cin => cin, + i0 => i0, + i1 => i1, + q => q_32, + cout => cout + ); + + process + + variable rva, rvb : integer; + + begin + cin <= '0'; + + loop_i0: for va in 0 to 15 loop + loop_i1: for vb in 0 to 15 loop + rva := rand_int(-200, 200); + rvb := rand_int(-200, 200); + i0 <= std_logic_vector(to_unsigned(va, 32)); + i1 <= std_logic_vector(to_unsigned(vb, 32)); + vadd <= std_logic_vector(to_unsigned(va+vb, 32)); + wait for 2 fs; + report "i0 : " & integer'image(to_integer(unsigned(i0))) + & " + i1 : " + & integer'image(to_integer(unsigned(i1))) + & " = " + & integer'image(to_integer(unsigned(q_32))) + & " ( vadd = " + & integer'image(to_integer(unsigned(vadd))) + & " ) "; + assert vadd = q_32 report "ERROR not equal !" severity error; + + end loop loop_i1; + end loop loop_i0; + wait; + end process; + +end Structurel; diff --git a/adder_32bit.vhdl b/adder_32bit.vhdl deleted file mode 100644 index 1c441bb..0000000 --- a/adder_32bit.vhdl +++ /dev/null @@ -1,53 +0,0 @@ -library ieee; -use ieee.math_real.all; -use ieee.numeric_std.all; -use ieee.std_logic_1164.all; - ------------------------------------------------------------------ --- ADDER 32 BIT ------------------------------------------------------------------ -ENTITY adder_32bit_ent IS -PORT ( - cin : IN std_logic; - i0, i1 : IN std_logic_vector(31 downto 0); - q : OUT std_logic_vector(31 downto 0); - cout : OUT std_logic -); -END ENTITY; ------------------------------------------------------------------ -ARCHITECTURE adder_32bit OF adder_32bit_ent IS - -SIGNAL co : std_logic_vector(31 downto 0); - -BEGIN -adder0 : entity work.adder1bit -PORT MAP ( - i0 => i0(0), - i1 => i1(0), - cin => cin, - q => q(0), - cout => co(0) -); - -loop_29: for i in 1 to 30 generate -adder_32bitN : entity work.adder1bit -PORT MAP ( - i0 => i0(i), - i1 => i1(i), - cin => co(i-1), - q => q(i), - cout => co(i) -); -END GENERATE loop_29; - -adder31 : entity work.adder1bit -PORT MAP ( - i0 => i0(31), - i1 => i1(31), - cin => co(30), - q => q(31), - cout => cout -); - -END adder_32bit; - diff --git a/adder_32bit_tb.vhdl b/adder_32bit_tb.vhdl deleted file mode 100644 index a7827c0..0000000 --- a/adder_32bit_tb.vhdl +++ /dev/null @@ -1,77 +0,0 @@ -LIBRARY ieee; -use ieee.math_real.all; -USE ieee.std_logic_1164.all; -use ieee.numeric_std.all; - ---- - -ENTITY adder_32bit_tb IS -END adder_32bit_tb; - ---- - -ARCHITECTURE Structurel OF adder_32bit_tb is -COMPONENT adder -PORT ( - cin : IN std_logic; - i0, i1 : IN std_logic_vector(31 downto 0); - q : OUT std_logic_vector(31 downto 0); - cout : OUT std_logic -); -END COMPONENT; - -SIGNAL cout, cin : std_logic; -SIGNAL i0, i1, q_32 : std_logic_vector(31 downto 0); -signal vadd : std_logic_vector(31 downto 0); - -impure function rand_int(min_val, max_val : integer) return integer is - variable r : real; - variable seed1, seed2 : integer := 998; -begin - uniform(seed1, seed2, r); - return integer( - round(r * real(max_val - min_val + 1) + real(min_val) - 0.5)); -end function; - -BEGIN -adder_0: entity work.adder_32bit_ent -PORT MAP( - cin => cin, - i0 => i0, - i1 => i1, - q => q_32, - cout => cout - ); - -process - -variable rva, rvb : integer; - -begin - -cin <= '0'; - -loop_i0: for va in 0 to 15 loop - loop_i1: for vb in 0 to 15 loop - rva := rand_int(-200, 200); - rvb := rand_int(-200, 200); - i0 <= std_logic_vector(to_unsigned(va, 32)); - i1 <= std_logic_vector(to_unsigned(vb, 32)); - vadd <= std_logic_vector(to_unsigned(va+vb, 32)); - wait for 2 fs; - REPORT "i0 : " & integer'image(to_integer(unsigned(i0))) - & " + i1 : " - & integer'image(to_integer(unsigned(i1))) - & " = " - & integer'image(to_integer(unsigned(q_32))) - & " ( vadd = " - & integer'image(to_integer(unsigned(vadd))) - & " ) "; - ASSERT vadd = q_32 REPORT "ERROR not equal !" SEVERITY ERROR; - - end loop loop_i1; -end loop loop_i0; -WAIT; -end process; - -END Structurel; diff --git a/adder_tb.vhdl b/adder_tb.vhdl deleted file mode 100644 index 1076f6e..0000000 --- a/adder_tb.vhdl +++ /dev/null @@ -1,45 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; -use ieee.numeric_std.all; - - -ENTITY adder_tb IS -END adder_tb; - -ARCHITECTURE Structurel OF adder_tb is -COMPONENT adder -PORT ( - i0, i1 : IN std_logic_vector(3 downto 0); - q : OUT std_logic_vector(3 downto 0) -); -END COMPONENT; - -SIGNAL i0, i1, q : std_logic_vector(3 downto 0); -signal vadd : std_logic_vector(3 downto 0); -BEGIN -adder_0: entity work.adder_4bit_ent -PORT MAP( i0 => i0, - i1 => i1, - q => q); - -process - -begin -loop_i0: for va in 0 to 15 loop - loop_i1: for vb in 0 to 15 loop - i0 <= std_logic_vector(to_unsigned(va, 4)); - i1 <= std_logic_vector(to_unsigned(vb, 4)); - vadd <= std_logic_vector(to_unsigned(va+vb, 4)); - REPORT "i0 : " & integer'image(to_integer(unsigned(i0))) - & " + i1 : " - & integer'image(to_integer(unsigned(i1))) - & " = " - & integer'image(to_integer(unsigned(q))); - ASSERT vadd = q REPORT "ERROR not equal !" SEVERITY ERROR; - wait for 2 fs; - end loop loop_i1; -end loop loop_i0; -WAIT; -end process; - -END Structurel; diff --git a/alu.vhdl b/alu.vhdl index 72015b3..16dc5bc 100644 --- a/alu.vhdl +++ b/alu.vhdl @@ -3,75 +3,77 @@ use ieee.math_real.all; use ieee.numeric_std.all; use ieee.std_logic_1164.all; -entity Alu is - port ( op1 : in Std_Logic_Vector(31 downto 0); - op2 : in Std_Logic_Vector(31 downto 0); - cin : in Std_Logic; - cmd : in Std_Logic_Vector(1 downto 0); - res : out Std_Logic_Vector(31 downto 0); - cout : out Std_Logic; - z : out Std_Logic; - n : out Std_Logic; - v : out Std_Logic; - vdd : in bit; - vss : in bit ); -end Alu; +entity ALU is + port ( + op1 : IN std_logic_vector(31 downto 0); + op2 : IN std_logic_vector(31 downto 0); + cin : IN std_logic; + cmd : IN std_logic_vector(1 downto 0); + res : out std_logic_vector(31 downto 0); + cout : out std_logic; + z : out std_logic; + n : out std_logic; + v : out std_logic; + vdd : IN bit; + vss : IN bit + ); +end ALU; -------------------------------------------------------------------------------- -architecture Alu_bhvr of Alu is - signal cout_temp, add_cout : std_logic; - signal res_temp, add : Std_Logic_Vector(31 downto 0); +architecture ALU_bhvr of ALU is + signal cout_temp, add_cout : std_logic; + signal res_temp, add : std_logic_vector(31 downto 0); - begin - - adder_0: entity work.adder_32bit_ent - PORT MAP( - cin => cin, - i0 => op1, - i1 => op2, - q => add, - cout => add_cout - ); +begin - process(op1, op2, cin, cmd, vss , vdd, add, add_cout) - begin - case cmd is - when "00" => + adder_0: entity work.adder32_ent + port map( + cin => cin, + i0 => op1, + i1 => op2, + q => add, + cout => add_cout + ); + + process(op1, op2, cin, cmd, vss , vdd, add, add_cout) + begin + case cmd is + when "00" => report "ADD"; res_temp <= add; cout_temp <= add_cout; - - when "01" => + + when "01" => report "AND"; res_temp <= op1 and op2 ; cout_temp <= '0'; - when "10" => + when "10" => report "OR "; res_temp <= op1 or op2; cout_temp <= '0'; - when "11" => + when "11" => report "XOR"; res_temp <= op1 xor op2 ; cout_temp <= '0'; - when others => + when others => report "ERROR"; - end case; - end process; + end case; + end process; - process(res_temp, cout_temp) - begin - - if (res_temp="00000000000000000000000000000000") - then z <= '1'; - else z <= '0'; - end if; + process(res_temp, cout_temp) + begin - n <= res_temp(31); - v <= res_temp(31) XOR cout_temp; + if (res_temp="00000000000000000000000000000000") + then z <= '1'; + else z <= '0'; + end if; + + n <= res_temp(31); + v <= res_temp(31) xor cout_temp; cout <= cout_temp; res <= res_temp; - end process; + end process; -end Alu_bhvr; +end ALU_bhvr; diff --git a/alu_tb.vhdl b/alu_tb.vhdl index 2ff3b48..d1d054d 100644 --- a/alu_tb.vhdl +++ b/alu_tb.vhdl @@ -3,109 +3,111 @@ use ieee.math_real.all; use ieee.numeric_std.all; use ieee.std_logic_1164.all; -entity alu_tb is -end alu_tb; +entity ALU_tb is +end ALU_tb; -ARCHITECTURE Structurel OF alu_tb is -signal op1 : Std_Logic_Vector(31 downto 0) := std_logic_vector(to_unsigned(32654, 32)); -signal op2 : Std_Logic_Vector(31 downto 0) := std_logic_vector(to_unsigned(65877, 32)); -signal cin : Std_Logic := '0'; -signal cmd : Std_Logic_Vector(1 downto 0) := "00"; -signal res : Std_Logic_Vector(31 downto 0) := (others => '0'); -signal cout : Std_Logic; -signal z : Std_Logic; -signal n : Std_Logic; -signal v : Std_Logic; -signal vdd : bit := '1'; -signal vss : bit := '0'; + +architecture Structurel of ALU_tb is + signal op1 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(32654, 32)); + signal op2 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(65877, 32)); + signal cin : std_logic := '0'; + signal cmd : std_logic_vector(1 downto 0) := "00"; + signal res : std_logic_vector(31 downto 0) := (others => '0'); + signal cout : std_logic; + signal z : std_logic; + signal n : std_logic; + signal v : std_logic; + signal vdd : bit := '1'; + signal vss : bit := '0'; begin -alu_ins: entity work.alu -PORT MAP( - op1 => op1, - op2 => op2, - cin => cin, - cmd => cmd, - res => res, - cout => cout, - z => z, - n => n, - v => v, - vdd => vdd, - vss => vss - ); -process -begin + ALU_ins: entity work.ALU + port map( + op1 => op1, + op2 => op2, + cin => cin, + cmd => cmd, + res => res, + cout => cout, + z => z, + n => n, + v => v, + vdd => vdd, + vss => vss + ); -wait for 5 fs; -cmd <= "00"; -wait for 5 fs; -report "op1 = " & integer'image(to_integer(unsigned(op1))); -report "op2 = " & integer'image(to_integer(unsigned(op2))); -report "res = " & integer'image(to_integer(unsigned(res))); -assert z/='1'report "z"; -assert n/='1'report "n"; -assert v/='1'report "v"; + process + begin -wait for 5 fs; + wait for 5 fs; + cmd <= "00"; + wait for 5 fs; + report "op1 = " & integer'image(to_integer(unsigned(op1))); + report "op2 = " & integer'image(to_integer(unsigned(op2))); + report "res = " & integer'image(to_integer(unsigned(res))); + assert z/='1'report "z"; + assert n/='1'report "n"; + assert v/='1'report "v"; -cmd <= "01"; -wait for 5 fs; -report "op1 = " & integer'image(to_integer(unsigned(op1))); -report "op2 = " & integer'image(to_integer(unsigned(op2))); -report "res = " & integer'image(to_integer(unsigned(res))); -assert z/='1'report "z"; -assert n/='1'report "n"; -assert v/='1'report "v"; + wait for 5 fs; -wait for 5 fs; + cmd <= "01"; + wait for 5 fs; + report "op1 = " & integer'image(to_integer(unsigned(op1))); + report "op2 = " & integer'image(to_integer(unsigned(op2))); + report "res = " & integer'image(to_integer(unsigned(res))); + assert z/='1'report "z"; + assert n/='1'report "n"; + assert v/='1'report "v"; -cmd <= "10"; -wait for 5 fs; -report "op1 = " & integer'image(to_integer(unsigned(op1))); -report "op2 = " & integer'image(to_integer(unsigned(op2))); -report "res = " & integer'image(to_integer(unsigned(res))); -assert z/='1'report "z"; -assert n/='1'report "n"; -assert v/='1'report "v"; + wait for 5 fs; -wait for 5 fs; + cmd <= "10"; + wait for 5 fs; + report "op1 = " & integer'image(to_integer(unsigned(op1))); + report "op2 = " & integer'image(to_integer(unsigned(op2))); + report "res = " & integer'image(to_integer(unsigned(res))); + assert z/='1'report "z"; + assert n/='1'report "n"; + assert v/='1'report "v"; -cmd <= "11"; -wait for 5 fs; -report "op1 = " & integer'image(to_integer(unsigned(op1))); -report "op2 = " & integer'image(to_integer(unsigned(op2))); -report "res = " & integer'image(to_integer(unsigned(res))); -assert z/='1'report "z"; -assert n/='1'report "n"; -assert v/='1'report "v"; + wait for 5 fs; -wait for 5 fs; -cmd <= "00"; -wait for 5 fs; -report "op1 = " & integer'image(to_integer(unsigned(op1))); -report "op2 = " & integer'image(to_integer(unsigned(op2))); -report "res = " & integer'image(to_integer(unsigned(res))); -assert z/='1'report "z"; -assert n/='1'report "n"; -assert v/='1'report "v"; + cmd <= "11"; + wait for 5 fs; + report "op1 = " & integer'image(to_integer(unsigned(op1))); + report "op2 = " & integer'image(to_integer(unsigned(op2))); + report "res = " & integer'image(to_integer(unsigned(res))); + assert z/='1'report "z"; + assert n/='1'report "n"; + assert v/='1'report "v"; + + wait for 5 fs; + cmd <= "00"; + wait for 5 fs; + report "op1 = " & integer'image(to_integer(unsigned(op1))); + report "op2 = " & integer'image(to_integer(unsigned(op2))); + report "res = " & integer'image(to_integer(unsigned(res))); + assert z/='1'report "z"; + assert n/='1'report "n"; + assert v/='1'report "v"; -wait for 5 fs; -cmd <= "00"; -wait for 5 fs; -report "op1 = " & integer'image(to_integer(unsigned(op1))); -report "op2 = " & integer'image(to_integer(unsigned(op2))); -report "res = " & integer'image(to_integer(unsigned(res))); -assert z/='1'report "z"; -assert n/='1'report "n"; -assert v/='1'report "v"; + wait for 5 fs; + cmd <= "00"; + wait for 5 fs; + report "op1 = " & integer'image(to_integer(unsigned(op1))); + report "op2 = " & integer'image(to_integer(unsigned(op2))); + report "res = " & integer'image(to_integer(unsigned(res))); + assert z/='1'report "z"; + assert n/='1'report "n"; + assert v/='1'report "v"; -wait for 50 fs; + wait for 50 fs; -WAIT; -end process; + wait; + end process; -END Structurel; +end Structurel;