54 lines
1.0 KiB
VHDL
54 lines
1.0 KiB
VHDL
library ieee;
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use ieee.math_real.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_1164.all;
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-----------------------------------------------------------------
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-- ADDER 32 BIT
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-----------------------------------------------------------------
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ENTITY adder_32bit_ent IS
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PORT (
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cin : IN std_logic;
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i0, i1 : IN std_logic_vector(31 downto 0);
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q : OUT std_logic_vector(31 downto 0);
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cout : OUT std_logic
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);
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END ENTITY;
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-----------------------------------------------------------------
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ARCHITECTURE adder_32bit OF adder_32bit_ent IS
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SIGNAL co : std_logic_vector(31 downto 0);
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BEGIN
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adder0 : entity work.adder1bit
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PORT MAP (
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i0 => i0(0),
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i1 => i1(0),
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cin => cin,
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q => q(0),
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cout => co(0)
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);
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loop_29: for i in 1 to 30 generate
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adder_32bitN : entity work.adder1bit
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PORT MAP (
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i0 => i0(i),
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i1 => i1(i),
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cin => co(i-1),
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q => q(i),
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cout => co(i)
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);
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END GENERATE loop_29;
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adder31 : entity work.adder1bit
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PORT MAP (
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i0 => i0(31),
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i1 => i1(31),
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cin => co(30),
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q => q(31),
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cout => cout
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);
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END adder_32bit;
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