library ieee;
use ieee.math_real.all;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;

-----------------------------------------------------------------
-- ADDER 32 BIT
-----------------------------------------------------------------
ENTITY adder_32bit_ent IS
PORT (
    cin     : IN    std_logic;
	i0, i1	: IN	std_logic_vector(31 downto 0);
	q		: OUT	std_logic_vector(31 downto 0);
	cout    : OUT   std_logic
);
END ENTITY;
-----------------------------------------------------------------
ARCHITECTURE adder_32bit OF adder_32bit_ent IS

SIGNAL co : std_logic_vector(31 downto 0);

BEGIN
adder0 : entity work.adder1bit
PORT MAP (
	i0 => i0(0),
	i1 => i1(0),
	cin => cin,
	q  => q(0),
	cout => co(0)
);

loop_29: for i in 1 to 30 generate 
adder_32bitN : entity work.adder1bit
PORT MAP (
	i0 => i0(i),
	i1 => i1(i),
	cin => co(i-1),
	q  => q(i),
	cout => co(i)
);
END GENERATE loop_29;

adder31 : entity work.adder1bit
PORT MAP (
	i0 => i0(31),
	i1 => i1(31),
	cin => co(30),
	q  => q(31),
	cout => cout
);

END adder_32bit;