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ALU_tb fonctionnel

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Adrien Bourmault 2021-12-10 15:45:56 +01:00
parent f1560a6556
commit 25f67ed707
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4 changed files with 8 additions and 7 deletions
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2
Makefile
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@ -1,5 +1,5 @@
GHDL = ghdl GHDL = ghdl
all : sim_alu #sim_shifter all : sim_alu sim_shifter
%.o : %.vhdl %.o : %.vhdl
${GHDL} -a -g -v $^ ${GHDL} -a -g -v $^

8
alu_tb.vhdl
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@ -3,10 +3,10 @@ use ieee.math_real.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
entity ALU is entity ALU_tb is
end ALU; end ALU_tb;
architecture Structurel of ALU is architecture Structurel of ALU_tb is
--! ######## signals for component ######## --! ######## signals for component ########
@ -33,7 +33,7 @@ architecture Structurel of ALU is
end function; end function;
begin begin
alu_0 : entity work.alu alu_0 : entity work.ALU
port map( port map(
op1 => op1, op1 => op1,
op2 => op2, op2 => op2,

1
shifter.vhdl
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@ -39,6 +39,7 @@ architecture Shifter_bhvr of Shifter is
begin begin
temp_dout := din; temp_dout := din;
temp_cout := cin; temp_cout := cin;
-- LSL ------------------------------------------------------------- -- LSL -------------------------------------------------------------
-- 1 -- 1
if(shift_lsl='1' and shift_val(0)='1') if(shift_lsl='1' and shift_val(0)='1')

4
shifter_tb.vhdl
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@ -39,8 +39,8 @@ port map(
process process
begin begin
shift_ror <= '1'; shift_ror <= '1';
shift_val <= "00010"; shift_val <= "00100";
din <= std_logic_vector(to_unsigned(32654, 32)); din <= std_logic_vector(to_unsigned(4, 32));
wait for 5 ns; wait for 5 ns;
report "dout = " & integer'image(to_integer(unsigned(dout))); report "dout = " & integer'image(to_integer(unsigned(dout)));
WAIT; WAIT;