diff --git a/Makefile b/Makefile
index a450fe7..6d23e60 100644
--- a/Makefile
+++ b/Makefile
@@ -1,5 +1,5 @@
 GHDL = ghdl
-all : sim_alu #sim_shifter
+all : sim_alu sim_shifter
 
 %.o : %.vhdl
 	${GHDL} -a -g -v $^
diff --git a/alu_tb.vhdl b/alu_tb.vhdl
index b1c3bc6..8140258 100644
--- a/alu_tb.vhdl
+++ b/alu_tb.vhdl
@@ -3,10 +3,10 @@ use ieee.math_real.all;
 use ieee.numeric_std.all;
 use ieee.std_logic_1164.all;
 
-entity ALU is
-end ALU;
+entity ALU_tb is
+end ALU_tb;
 
-architecture Structurel of ALU is
+architecture Structurel of ALU_tb is
 
   --! ########   signals for component    ########
  
@@ -33,7 +33,7 @@ architecture Structurel of ALU is
   end function;
 
 begin
-  alu_0 : entity work.alu
+  alu_0 : entity work.ALU
     port map(
       op1  => op1,
       op2  => op2,
diff --git a/shifter.vhdl b/shifter.vhdl
index c31e11e..3abbd1c 100644
--- a/shifter.vhdl
+++ b/shifter.vhdl
@@ -39,6 +39,7 @@ architecture Shifter_bhvr of Shifter is
             begin
             temp_dout := din;
             temp_cout := cin;
+            
             -- LSL -------------------------------------------------------------
             -- 1
             if(shift_lsl='1' and shift_val(0)='1') 
diff --git a/shifter_tb.vhdl b/shifter_tb.vhdl
index fc43d87..0d96093 100644
--- a/shifter_tb.vhdl
+++ b/shifter_tb.vhdl
@@ -39,8 +39,8 @@ port map(
 process
 begin
     shift_ror <= '1';
-    shift_val <= "00010";
-    din       <= std_logic_vector(to_unsigned(32654, 32));
+    shift_val <= "00100";
+    din       <= std_logic_vector(to_unsigned(4, 32));
     wait for 5 ns;
     report "dout = " & integer'image(to_integer(unsigned(dout)));
     WAIT;