projet-vlsi/alu.vhdl

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VHDL
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library ieee;
use ieee.math_real.all;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
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entity ALU is
port (
op1 : IN std_logic_vector(31 downto 0);
op2 : IN std_logic_vector(31 downto 0);
cin : IN std_logic;
cmd : IN std_logic_vector(1 downto 0);
res : out std_logic_vector(31 downto 0);
cout : out std_logic;
z : out std_logic;
n : out std_logic;
v : out std_logic;
vdd : IN bit;
vss : IN bit
);
end ALU;
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--------------------------------------------------------------------------------
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architecture ALU_bhvr of ALU is
signal cout_temp, add_cout : std_logic;
signal res_temp, add : std_logic_vector(31 downto 0);
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begin
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adder_0: entity work.adder32_ent
port map(
cin => cin,
i0 => op1,
i1 => op2,
q => add,
cout => add_cout
);
process(op1, op2, cin, cmd, vss , vdd, add, add_cout)
begin
case cmd is
when "00" =>
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-- report "ADD";
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res_temp <= add;
cout_temp <= add_cout;
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when "01" =>
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-- report "AND";
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res_temp <= op1 and op2 ;
cout_temp <= '0';
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when "10" =>
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-- report "OR ";
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res_temp <= op1 or op2;
cout_temp <= '0';
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when "11" =>
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-- report "XOR";
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res_temp <= op1 xor op2 ;
cout_temp <= '0';
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when others =>
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report "[ERROR] SWITCH CASE UNREACHABLE (Alu::cmd not initialised ?)";
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end case;
end process;
process(res_temp, cout_temp)
begin
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if (res_temp="00000000000000000000000000000000")
then z <= '1';
else z <= '0';
end if;
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n <= res_temp(31);
v <= res_temp(31) xor cout_temp;
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cout <= cout_temp;
res <= res_temp;
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end process;
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end ALU_bhvr;
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