projet-vlsi/exec_tb.vhdl

library ieee;
use ieee.math_real.all;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;

entity exec_tb is
end exec_tb;


architecture Structurel of exec_tb is

			signal dec2exe_empty	:  Std_logic;
			signal exe_pop			:  Std_logic;
			signal dec_op1			:  Std_Logic_Vector(31 downto 0); -- first alu input
			signal dec_op2			:  Std_Logic_Vector(31 downto 0); -- shifter input
			signal dec_exe_dest	:  Std_Logic_Vector(3 downto 0) ; -- Rd destination
			signal dec_exe_wb		:  Std_Logic; -- Rd destination write back
			signal dec_flag_wb		:  Std_Logic; -- CSPR modifiy
			signal dec_mem_data	:  Std_Logic_Vector(31 downto 0); -- data to MEM W
			signal dec_mem_dest	:  Std_Logic_Vector(3 downto 0) ; -- Destination MEM R
			signal dec_pre_index 	:  Std_logic;
			signal dec_mem_lw		:  Std_Logic;
			signal dec_mem_lb		:  Std_Logic;
			signal dec_mem_sw		:  Std_Logic;
			signal dec_mem_sb		:  Std_Logic;
			signal dec_shift_lsl	:  Std_Logic;
			signal dec_shift_lsr	:  Std_Logic;
			signal dec_shift_asr	:  Std_Logic;
			signal dec_shift_ror	:  Std_Logic;
			signal dec_shift_rrx	:  Std_Logic;
			signal dec_shift_val	:  Std_Logic_Vector(4 downto 0);
			signal dec_cy			:  Std_Logic;
			signal dec_comp_op1	:  Std_Logic;
			signal dec_comp_op2	:  Std_Logic;
			signal dec_alu_cy 		:  Std_Logic;
			signal dec_alu_cmd		:  Std_Logic_Vector(1 downto 0);
			signal exe_res			:  Std_Logic_Vector(31 downto 0);
			signal exe_c			:  Std_Logic;
			signal exe_v			:  Std_Logic;
			signal exe_n			:  Std_Logic;
			signal exe_z		    :  Std_Logic;
			signal exe_dest		:  Std_Logic_Vector(3 downto 0); -- Rd destination
			signal exe_wb			:  Std_Logic; -- Rd destination write back
			signal exe_flag_wb		:  Std_Logic; -- CSPR modifiy
			signal exe_mem_adr		:  Std_Logic_Vector(31 downto 0); -- Alu res register
			signal exe_mem_data	:  Std_Logic_Vector(31 downto 0);
			signal exe_mem_dest	:  Std_Logic_Vector(3 downto 0);
			signal exe_mem_lw		:  Std_Logic;
			signal exe_mem_lb		:  Std_Logic;
			signal exe_mem_sw		:  Std_Logic;
			signal exe_mem_sb		:  Std_Logic;
			signal exe2mem_empty	:  Std_logic;
			signal mem_pop			:  Std_logic;
			signal ck				:  Std_logic := '0';
			signal reset_n			:  Std_logic;
			signal vdd				:  bit;
			signal vss				:  bit;
begin


	ALU_ins: entity work.exec
	port map(
			dec2exe_empty => dec2exe_empty,
			exe_pop => exe_pop,
			dec_op1 => dec_op1,
			dec_op2 => dec_op2,
			dec_exe_dest => dec_exe_dest,
			dec_exe_wb => dec_exe_wb,
			dec_flag_wb => dec_flag_wb,
			dec_mem_data => dec_mem_data,
			dec_mem_dest => dec_mem_dest,
			dec_pre_index => dec_pre_index,
			dec_mem_lw => dec_mem_lw,
			dec_mem_lb => dec_mem_lb,
			dec_mem_sw => dec_mem_sw,
			dec_mem_sb => dec_mem_sb,
			dec_shift_lsl => dec_shift_lsl,
			dec_shift_lsr => dec_shift_lsr,
			dec_shift_asr => dec_shift_asr,
			dec_shift_ror => dec_shift_ror,
			dec_shift_rrx => dec_shift_rrx,
			dec_shift_val => dec_shift_val,
			dec_cy => dec_cy,
			dec_comp_op1 => dec_comp_op1,
			dec_comp_op2 => dec_comp_op2,
			dec_alu_cy => dec_alu_cy,
			dec_alu_cmd => dec_alu_cmd,
			exe_res => exe_res,
			exe_c => exe_c,
			exe_v => exe_v,
			exe_n => exe_n,
			exe_z => exe_z,
			exe_dest => exe_dest,
			exe_wb => exe_wb,
			exe_flag_wb => exe_flag_wb,
			exe_mem_adr => exe_mem_adr,
			exe_mem_data => exe_mem_data,
			exe_mem_dest => exe_mem_dest,
			exe_mem_lw => exe_mem_lw,
			exe_mem_lb => exe_mem_lb,
			exe_mem_sw => exe_mem_sw,
			exe_mem_sb => exe_mem_sb,
			exe2mem_empty => exe2mem_empty,
			mem_pop => mem_pop,
			ck => ck,
			reset_n => reset_n,
			vdd => vdd,
			vss => vss 
		);
	
	-- HOLORGE
	
	ck <= not ck after 2 ns;
	process
	begin
		-- decode interface synchro
		dec2exe_empty <= '0';
		-- decode interface operands
		dec_op1 <= x"00000005"; --important
		dec_op2 <= x"00000000"; --important
		dec_exe_dest <= x"1";
		dec_exe_wb <= '1';
		dec_flag_wb <= '1';
		-- decode to mem interface
		dec_mem_data <= x"00000000";
		dec_mem_dest <= x"2";
		dec_pre_index <= '1'; -- important
		dec_mem_lw <= '0';
		dec_mem_lb <= '0';
		dec_mem_sw <= '0';
		dec_mem_sb <= '0';
		--shifter command
		dec_shift_lsl <= '0';
		dec_shift_lsr <= '0';
		dec_shift_asr <= '0';
		dec_shift_ror <= '0';
		dec_shift_rrx <= '0';
		dec_shift_val <= "00000";
		dec_cy  <= '0';
		-- Alu operand selection
		dec_comp_op1	<= '0';
		dec_comp_op2	<= '0';
		dec_alu_cy 		<= '0';
		-- alu command
		dec_alu_cmd  <= "01";
		-- mem interface
		mem_pop  <= '0';
		reset_n <= '1';
		vdd <= '1';
		vss <= '0';

		wait for 10 ns;
		-- addition de 2 et 1
		dec_op1 <= x"00000002";
		dec_op2 <= x"00000001";
		dec_pre_index <= '0'; -- si 1 op1 si 0 op1 <OP> op2  
		--
		dec_shift_lsl <= '0';
		dec_shift_lsr <= '0';
		dec_shift_asr <= '0';
		dec_shift_ror <= '0';
		dec_shift_rrx <= '0';
		dec_shift_val <= "00000";
		dec_cy  <= '0';
		---
		dec_comp_op1	<= '0'; -- ~op1
		dec_comp_op2	<= '0'; -- ~op2
		dec_alu_cy 		<= '0'; -- carry complement a 2 les ops
		dec_alu_cmd     <= "00";-- commande "00" == add
		
		wait for 10 ns;
		assert exe_res = x"00000003" report "ERROR EXEC addition (2 et 1)" severity FAILURE;

		-- soustraction de 3 et 1
		dec_op1 <= x"00000002";
		dec_op2 <= x"00000001";
		dec_pre_index <= '0'; -- si 1 op1 si 0 op1 <OP> op2  
		--
		dec_shift_lsl <= '0';
		dec_shift_lsr <= '0';
		dec_shift_asr <= '0';
		dec_shift_ror <= '0';
		dec_shift_rrx <= '0';
		dec_shift_val <= "00000";
		dec_cy  <= '0';
		---
		dec_comp_op1	<= '0'; -- ~op1
		dec_comp_op2	<= '1'; -- ~op2
		dec_alu_cy 		<= '1'; -- carry complement a 2 les ops
		dec_alu_cmd     <= "00";-- commande "00" == add
		wait for 10 ns;
		assert exe_res = x"00000001" report "ERROR EXEC addition (2 et -1)" severity FAILURE;
		
		-- soustraction de 1 et 3
		dec_op1 <= x"00000001";
		dec_op2 <= x"00000003";
		dec_pre_index <= '0'; -- si 1 op1 si 0 op1 <OP> op2  
		--
		dec_shift_lsl <= '0';
		dec_shift_lsr <= '0';
		dec_shift_asr <= '0';
		dec_shift_ror <= '0';
		dec_shift_rrx <= '0';
		dec_shift_val <= "00000";
		dec_cy  <= '0';
		---
		dec_comp_op1	<= '0'; -- ~op1
		dec_comp_op2	<= '1'; -- ~op2
		dec_alu_cy 		<= '1'; -- carry complement a 2 les ops
		dec_alu_cmd     <= "00";-- commande "00" == add
		wait for 10 ns;
		-- FFFFFFFE => -2
		assert exe_res = x"FFFFFFFE" report "ERROR EXEC addition (1 et -3)" severity FAILURE;

		-- soustraction de 1 et 8 (1 avec shift de 3)
		dec_op1 <= x"00000001";
		dec_op2 <= x"00000001";
		dec_pre_index <= '0'; -- si 1 op1 si 0 op1 <OP> op2  
		--
		dec_shift_lsl <= '1'; -- left shift
		dec_shift_lsr <= '0';
		dec_shift_asr <= '0';
		dec_shift_ror <= '0';
		dec_shift_rrx <= '0';
		dec_shift_val <= "00011"; -- decalage de 3
		dec_cy  <= '0';
		---
		dec_comp_op1	<= '0'; -- op1
		dec_comp_op2	<= '1'; -- ~op2
		dec_alu_cy 		<= '1'; -- carry complement a 2 les ops
		dec_alu_cmd     <= "00";-- commande "00" == add
		wait for 10 ns;
		-- FFFFFFF9 => -7
		assert exe_res = x"FFFFFFF9" report "ERROR EXEC addition (1 et -3)" severity FAILURE;
		
		report "fin simu" severity FAILURE;
	end process;

end Structurel;