exec mainly done, updated the makefile and fixed typos
This commit is contained in:
shaithan
parent
a80fc8c54f
commit
1740bb2139
8
Makefile
8
Makefile
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@ -7,12 +7,15 @@ all : sim_alu #sim_shifter
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adder32_tb : adder1.o adder32.o adder32_tb.o
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${GHDL} -e -v adder32_tb
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shifter_tb : shitfter.o shitfter_tb.o
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shifter_tb : shifter.o shifter_tb.o
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${GHDL} -e -v shifter_tb
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alu_tb : adder1.o adder32.o alu.o alu_tb.o
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${GHDL} -e -v alu_tb
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exec_tb :adder1.o adder32.o alu.o fifo_72b.o shifter.o exec.o exec_tb.o
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${GHDL} -e -v exec_tb
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sim_adder32 : adder32_tb
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${GHDL} -r adder32_tb --vcd=adder32.vcd
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@ -22,5 +25,8 @@ sim_alu : alu_tb
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sim_shifter : shifter_tb
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${GHDL} -r shifter_tb --vcd=shifter.vcd
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sim_exec : exec_tb
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${GHDL} -r exec_tb --vcd=exec.vcd
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clean :
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-rm *.o work-obj93.cf *_tb *.vcd
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@ -0,0 +1,254 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity EXec is
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port(
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-- Decode interface synchro
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dec2exe_empty : in Std_logic;
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exe_pop : out Std_logic;
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-- Decode interface operands
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dec_op1 : in Std_Logic_Vector(31 downto 0); -- first alu input
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dec_op2 : in Std_Logic_Vector(31 downto 0); -- shifter input
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dec_exe_dest : in Std_Logic_Vector(3 downto 0) ; -- Rd destination
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dec_exe_wb : in Std_Logic; -- Rd destination write back
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dec_flag_wb : in Std_Logic; -- CSPR modifiy
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-- Decode to mem interface
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dec_mem_data : in Std_Logic_Vector(31 downto 0); -- data to MEM W
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dec_mem_dest : in Std_Logic_Vector(3 downto 0) ; -- Destination MEM R
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dec_pre_index : in Std_logic;
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dec_mem_lw : in Std_Logic;
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dec_mem_lb : in Std_Logic;
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dec_mem_sw : in Std_Logic;
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dec_mem_sb : in Std_Logic;
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-- Shifter command
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dec_shift_lsl : in Std_Logic;
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dec_shift_lsr : in Std_Logic;
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dec_shift_asr : in Std_Logic;
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dec_shift_ror : in Std_Logic;
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dec_shift_rrx : in Std_Logic;
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dec_shift_val : in Std_Logic_Vector(4 downto 0);
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dec_cy : in Std_Logic;
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-- Alu operand selection
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dec_comp_op1 : in Std_Logic;
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dec_comp_op2 : in Std_Logic;
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dec_alu_cy : in Std_Logic;
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-- Alu command
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dec_alu_cmd : in Std_Logic_Vector(1 downto 0);
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-- Exe bypass to decod
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exe_res : out Std_Logic_Vector(31 downto 0);
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exe_c : out Std_Logic;
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exe_v : out Std_Logic;
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exe_n : out Std_Logic;
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exe_z : out Std_Logic;
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exe_dest : out Std_Logic_Vector(3 downto 0); -- Rd destination
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exe_wb : out Std_Logic; -- Rd destination write back
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exe_flag_wb : out Std_Logic; -- CSPR modifiy
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-- Mem interface
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exe_mem_adr : out Std_Logic_Vector(31 downto 0); -- Alu res register
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exe_mem_data : out Std_Logic_Vector(31 downto 0);
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exe_mem_dest : out Std_Logic_Vector(3 downto 0);
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exe_mem_lw : out Std_Logic;
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exe_mem_lb : out Std_Logic;
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exe_mem_sw : out Std_Logic;
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exe_mem_sb : out Std_Logic;
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exe2mem_empty : out Std_logic;
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mem_pop : in Std_logic;
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-- global interface
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ck : in Std_logic;
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reset_n : in Std_logic;
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vdd : in bit;
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vss : in bit);
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end EXec;
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----------------------------------------------------------------------
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architecture Behavior OF EXec is
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-- creation des components utilisés par EXEC
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component alu
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port ( op1 : in Std_Logic_Vector(31 downto 0);
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op2 : in Std_Logic_Vector(31 downto 0);
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cin : in Std_Logic;
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cmd : in Std_Logic_Vector(1 downto 0);
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res : out Std_Logic_Vector(31 downto 0);
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cout : out Std_Logic;
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z : out Std_Logic;
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n : out Std_Logic;
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v : out Std_Logic;
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vdd : in bit;
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vss : in bit);
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end component;
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component shifter
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port (
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shift_lsl : in Std_Logic;
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shift_lsr : in Std_Logic;
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shift_asr : in Std_Logic;
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shift_ror : in Std_Logic; -- rotation sans extension
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shift_rrx : in Std_Logic; -- avec extension
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shift_val : in Std_Logic_Vector(4 downto 0);
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din : in Std_Logic_Vector(31 downto 0);
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cin : in Std_Logic;
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dout : out Std_Logic_Vector(31 downto 0);
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cout : out Std_Logic;
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-- global interface
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vdd : in bit;
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vss : in bit
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);
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end component;
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component fifo_72b
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port(
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din : in std_logic_vector(71 downto 0);
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dout : out std_logic_vector(71 downto 0);
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-- commands
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push : in std_logic;
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pop : in std_logic;
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-- flags
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full : out std_logic;
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empty : out std_logic;
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reset_n : in std_logic;
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ck : in std_logic;
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vdd : in bit;
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vss : in bit
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);
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end component;
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-- signal reliant les instances
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-- signal sortant du shifter
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signal shifter_op2 : std_logic_vector(31 downto 0);
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signal shifter_op2_carry : std_logic;
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-- signal entrant de l'alu
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signal alu_op1_in, alu_op2_in : std_logic_vector(31 downto 0);
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-- signal sortant de l'alu
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signal alu_value_out : std_logic_vector(31 downto 0);
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signal alu_value_cout : std_logic;
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-- signal entrant fifo
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signal mem_adr : std_logic_vector(31 downto 0);
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signal exe_push, exe2mem_full : std_logic;
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begin
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-- Component instantiation.
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-- shifter
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shifter_int : shifter
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port map (
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shift_lsl => dec_shift_lsl,
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shift_lsr => dec_shift_lsr,
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shift_asr => dec_shift_asr,
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shift_ror => dec_shift_ror,
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shift_rrx => dec_shift_rrx,
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shift_val => dec_shift_val,
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din => dec_op2,
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cin => dec_cy,
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dout => shifter_op2,
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cout => shifter_op2_carry,
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-- global interface
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vdd => vdd,
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vss => vss
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);
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-- l'alu
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alu_inst : alu
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port map (
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op1 => alu_op1_in,
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op2 => alu_op2_in,
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cin => dec_alu_cy,
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cmd => dec_alu_cmd,
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res => alu_value_out,
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cout => alu_value_cout,
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z => exe_z,
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n => exe_n,
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v => exe_v,
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-- global interface
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vdd => vdd,
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vss => vss
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);
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-- étage de pipeline entre exec et mem
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exec2mem : fifo_72b
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port map ( din(71) => dec_mem_lw,
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din(70) => dec_mem_lb,
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din(69) => dec_mem_sw,
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din(68) => dec_mem_sb,
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din(67 downto 64) => dec_mem_dest,
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din(63 downto 32) => dec_mem_data,
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din(31 downto 0) => mem_adr,
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dout(71) => exe_mem_lw,
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dout(70) => exe_mem_lb,
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dout(69) => exe_mem_sw,
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dout(68) => exe_mem_sb,
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dout(67 downto 64) => exe_mem_dest,
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dout(63 downto 32) => exe_mem_data,
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dout(31 downto 0) => exe_mem_adr,
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push => exe_push,
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pop => mem_pop,
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empty => exe2mem_empty,
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full => exe2mem_full,
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reset_n => reset_n,
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ck => ck,
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vdd => vdd,
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vss => vss
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);
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-- multiplexeurs entrée ALU
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alu_op1_in <= (not dec_op1) when dec_comp_op1='1' else dec_op1;
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alu_op2_in <= (not shifter_op2) when dec_comp_op2='1' else shifter_op2;
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-- bypass 2 decod
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-- resultat ALU
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exe_res <= alu_value_out;
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-- carry flag
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exe_c <= alu_value_cout;
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-- sortie mutex entre ALU et fifo
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mem_adr <= (dec_op1) when dec_pre_index='1' else alu_value_out;
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-- Sortie restante
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-- exe_pop <= dec2exe_empty;
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-- exe_dest <= dec_exe_dest;
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-- exe_wb <= dec_exe_wb;
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-- exe_flag_wb <= dec_flag_wb;
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end Behavior;
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@ -0,0 +1,239 @@
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library ieee;
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use ieee.math_real.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_1164.all;
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entity exec_tb is
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end exec_tb;
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architecture Structurel of exec_tb is
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signal dec2exe_empty : Std_logic;
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signal exe_pop : Std_logic;
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signal dec_op1 : Std_Logic_Vector(31 downto 0); -- first alu input
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signal dec_op2 : Std_Logic_Vector(31 downto 0); -- shifter input
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signal dec_exe_dest : Std_Logic_Vector(3 downto 0) ; -- Rd destination
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signal dec_exe_wb : Std_Logic; -- Rd destination write back
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signal dec_flag_wb : Std_Logic; -- CSPR modifiy
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signal dec_mem_data : Std_Logic_Vector(31 downto 0); -- data to MEM W
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signal dec_mem_dest : Std_Logic_Vector(3 downto 0) ; -- Destination MEM R
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signal dec_pre_index : Std_logic;
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signal dec_mem_lw : Std_Logic;
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signal dec_mem_lb : Std_Logic;
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signal dec_mem_sw : Std_Logic;
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signal dec_mem_sb : Std_Logic;
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signal dec_shift_lsl : Std_Logic;
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signal dec_shift_lsr : Std_Logic;
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signal dec_shift_asr : Std_Logic;
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signal dec_shift_ror : Std_Logic;
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signal dec_shift_rrx : Std_Logic;
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signal dec_shift_val : Std_Logic_Vector(4 downto 0);
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signal dec_cy : Std_Logic;
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signal dec_comp_op1 : Std_Logic;
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signal dec_comp_op2 : Std_Logic;
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signal dec_alu_cy : Std_Logic;
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signal dec_alu_cmd : Std_Logic_Vector(1 downto 0);
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signal exe_res : Std_Logic_Vector(31 downto 0);
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signal exe_c : Std_Logic;
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signal exe_v : Std_Logic;
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signal exe_n : Std_Logic;
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signal exe_z : Std_Logic;
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signal exe_dest : Std_Logic_Vector(3 downto 0); -- Rd destination
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signal exe_wb : Std_Logic; -- Rd destination write back
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signal exe_flag_wb : Std_Logic; -- CSPR modifiy
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signal exe_mem_adr : Std_Logic_Vector(31 downto 0); -- Alu res register
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signal exe_mem_data : Std_Logic_Vector(31 downto 0);
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signal exe_mem_dest : Std_Logic_Vector(3 downto 0);
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signal exe_mem_lw : Std_Logic;
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signal exe_mem_lb : Std_Logic;
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signal exe_mem_sw : Std_Logic;
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signal exe_mem_sb : Std_Logic;
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signal exe2mem_empty : Std_logic;
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signal mem_pop : Std_logic;
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signal ck : Std_logic := '0';
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signal reset_n : Std_logic;
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signal vdd : bit;
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signal vss : bit;
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begin
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ALU_ins: entity work.exec
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port map(
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dec2exe_empty => dec2exe_empty,
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exe_pop => exe_pop,
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dec_op1 => dec_op1,
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dec_op2 => dec_op2,
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dec_exe_dest => dec_exe_dest,
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dec_exe_wb => dec_exe_wb,
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dec_flag_wb => dec_flag_wb,
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dec_mem_data => dec_mem_data,
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dec_mem_dest => dec_mem_dest,
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dec_pre_index => dec_pre_index,
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dec_mem_lw => dec_mem_lw,
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dec_mem_lb => dec_mem_lb,
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dec_mem_sw => dec_mem_sw,
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dec_mem_sb => dec_mem_sb,
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dec_shift_lsl => dec_shift_lsl,
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dec_shift_lsr => dec_shift_lsr,
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dec_shift_asr => dec_shift_asr,
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dec_shift_ror => dec_shift_ror,
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dec_shift_rrx => dec_shift_rrx,
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dec_shift_val => dec_shift_val,
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dec_cy => dec_cy,
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dec_comp_op1 => dec_comp_op1,
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dec_comp_op2 => dec_comp_op2,
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dec_alu_cy => dec_alu_cy,
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dec_alu_cmd => dec_alu_cmd,
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exe_res => exe_res,
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exe_c => exe_c,
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exe_v => exe_v,
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exe_n => exe_n,
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exe_z => exe_z,
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exe_dest => exe_dest,
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exe_wb => exe_wb,
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exe_flag_wb => exe_flag_wb,
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exe_mem_adr => exe_mem_adr,
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exe_mem_data => exe_mem_data,
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exe_mem_dest => exe_mem_dest,
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exe_mem_lw => exe_mem_lw,
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exe_mem_lb => exe_mem_lb,
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exe_mem_sw => exe_mem_sw,
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exe_mem_sb => exe_mem_sb,
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exe2mem_empty => exe2mem_empty,
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mem_pop => mem_pop,
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ck => ck,
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reset_n => reset_n,
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vdd => vdd,
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vss => vss
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);
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-- HOLORGE
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ck <= not ck after 2 ns;
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process
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begin
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-- decode interface synchro
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dec2exe_empty <= '0';
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-- decode interface operands
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dec_op1 <= x"00000005"; --important
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dec_op2 <= x"00000000"; --important
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dec_exe_dest <= x"1";
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dec_exe_wb <= '1';
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dec_flag_wb <= '1';
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-- decode to mem interface
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dec_mem_data <= x"00000000";
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dec_mem_dest <= x"2";
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dec_pre_index <= '1'; -- important
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dec_mem_lw <= '0';
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dec_mem_lb <= '0';
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dec_mem_sw <= '0';
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dec_mem_sb <= '0';
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--shifter command
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dec_shift_lsl <= '0';
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dec_shift_lsr <= '0';
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dec_shift_asr <= '0';
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dec_shift_ror <= '0';
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dec_shift_rrx <= '0';
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dec_shift_val <= "00000";
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dec_cy <= '0';
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-- Alu operand selection
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dec_comp_op1 <= '0';
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dec_comp_op2 <= '0';
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dec_alu_cy <= '0';
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-- alu command
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dec_alu_cmd <= "01";
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-- mem interface
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mem_pop <= '0';
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reset_n <= '1';
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vdd <= '1';
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vss <= '0';
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wait for 10 ns;
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-- addition de 2 et 1
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dec_op1 <= x"00000002";
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dec_op2 <= x"00000001";
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dec_pre_index <= '0'; -- si 1 op1 si 0 op1 <OP> op2
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--
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dec_shift_lsl <= '0';
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dec_shift_lsr <= '0';
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dec_shift_asr <= '0';
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dec_shift_ror <= '0';
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dec_shift_rrx <= '0';
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dec_shift_val <= "00000";
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dec_cy <= '0';
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---
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dec_comp_op1 <= '0'; -- ~op1
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dec_comp_op2 <= '0'; -- ~op2
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dec_alu_cy <= '0'; -- carry complement a 2 les ops
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dec_alu_cmd <= "00";-- commande "00" == add
|
||||
|
||||
wait for 10 ns;
|
||||
assert exe_res = x"00000003" report "ERROR EXEC addition (2 et 1)" severity FAILURE;
|
||||
|
||||
-- soustraction de 3 et 1
|
||||
dec_op1 <= x"00000002";
|
||||
dec_op2 <= x"00000001";
|
||||
dec_pre_index <= '0'; -- si 1 op1 si 0 op1 <OP> op2
|
||||
--
|
||||
dec_shift_lsl <= '0';
|
||||
dec_shift_lsr <= '0';
|
||||
dec_shift_asr <= '0';
|
||||
dec_shift_ror <= '0';
|
||||
dec_shift_rrx <= '0';
|
||||
dec_shift_val <= "00000";
|
||||
dec_cy <= '0';
|
||||
---
|
||||
dec_comp_op1 <= '0'; -- ~op1
|
||||
dec_comp_op2 <= '1'; -- ~op2
|
||||
dec_alu_cy <= '1'; -- carry complement a 2 les ops
|
||||
dec_alu_cmd <= "00";-- commande "00" == add
|
||||
wait for 10 ns;
|
||||
assert exe_res = x"00000001" report "ERROR EXEC addition (2 et -1)" severity FAILURE;
|
||||
|
||||
-- soustraction de 1 et 3
|
||||
dec_op1 <= x"00000001";
|
||||
dec_op2 <= x"00000003";
|
||||
dec_pre_index <= '0'; -- si 1 op1 si 0 op1 <OP> op2
|
||||
--
|
||||
dec_shift_lsl <= '0';
|
||||
dec_shift_lsr <= '0';
|
||||
dec_shift_asr <= '0';
|
||||
dec_shift_ror <= '0';
|
||||
dec_shift_rrx <= '0';
|
||||
dec_shift_val <= "00000";
|
||||
dec_cy <= '0';
|
||||
---
|
||||
dec_comp_op1 <= '0'; -- ~op1
|
||||
dec_comp_op2 <= '1'; -- ~op2
|
||||
dec_alu_cy <= '1'; -- carry complement a 2 les ops
|
||||
dec_alu_cmd <= "00";-- commande "00" == add
|
||||
wait for 10 ns;
|
||||
-- FFFFFFFE => -2
|
||||
assert exe_res = x"FFFFFFFE" report "ERROR EXEC addition (1 et -3)" severity FAILURE;
|
||||
|
||||
-- soustraction de 1 et 8 (1 avec shift de 3)
|
||||
dec_op1 <= x"00000001";
|
||||
dec_op2 <= x"00000001";
|
||||
dec_pre_index <= '0'; -- si 1 op1 si 0 op1 <OP> op2
|
||||
--
|
||||
dec_shift_lsl <= '1'; -- left shift
|
||||
dec_shift_lsr <= '0';
|
||||
dec_shift_asr <= '0';
|
||||
dec_shift_ror <= '0';
|
||||
dec_shift_rrx <= '0';
|
||||
dec_shift_val <= "00011"; -- decalage de 3
|
||||
dec_cy <= '0';
|
||||
---
|
||||
dec_comp_op1 <= '0'; -- op1
|
||||
dec_comp_op2 <= '1'; -- ~op2
|
||||
dec_alu_cy <= '1'; -- carry complement a 2 les ops
|
||||
dec_alu_cmd <= "00";-- commande "00" == add
|
||||
wait for 10 ns;
|
||||
-- FFFFFFF9 => -7
|
||||
assert exe_res = x"FFFFFFF9" report "ERROR EXEC addition (1 et -3)" severity FAILURE;
|
||||
|
||||
report "fin simu" severity FAILURE;
|
||||
end process;
|
||||
|
||||
end Structurel;
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
LIBRARY ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
ENTITY fifo IS
|
||||
PORT(
|
||||
din : in std_logic_vector(71 downto 0);
|
||||
dout : out std_logic_vector(71 downto 0);
|
||||
|
||||
-- commands
|
||||
push : in std_logic;
|
||||
pop : in std_logic;
|
||||
|
||||
-- flags
|
||||
full : out std_logic;
|
||||
empty : out std_logic;
|
||||
|
||||
reset_n : in std_logic;
|
||||
ck : in std_logic;
|
||||
vdd : in bit;
|
||||
vss : in bit
|
||||
);
|
||||
END fifo;
|
||||
|
||||
architecture dataflow of fifo is
|
||||
|
||||
signal fifo_d : std_logic_vector(71 downto 0);
|
||||
signal fifo_v : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
process(ck)
|
||||
begin
|
||||
if rising_edge(ck) then
|
||||
-- Valid bit
|
||||
if reset_n = '0' then
|
||||
fifo_v <= '0';
|
||||
else
|
||||
if fifo_v = '0' then
|
||||
if push = '1' then
|
||||
fifo_v <= '1';
|
||||
else
|
||||
fifo_v <= '0';
|
||||
end if;
|
||||
else
|
||||
if pop = '1' then
|
||||
if push = '1' then
|
||||
fifo_v <= '1';
|
||||
else
|
||||
fifo_v <= '0';
|
||||
end if;
|
||||
else
|
||||
fifo_v <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- data
|
||||
if fifo_v = '0' then
|
||||
if push = '1' then
|
||||
fifo_d <= din;
|
||||
end if;
|
||||
elsif push='1' and pop='1' then
|
||||
fifo_d <= din;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
full <= '1' when fifo_v = '1' and pop = '0' else '0';
|
||||
empty <= not fifo_v;
|
||||
dout <= fifo_d;
|
||||
|
||||
end dataflow;
|
||||
Loading…
Reference in New Issue