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Maj du 4/04

This commit is contained in:
Adrien Bourmault 2022-05-09 08:41:51 +02:00
parent de449bfa88
commit babf8f69bb
No known key found for this signature in database
GPG Key ID: 6EB408FE0ACEC664
17 changed files with 262 additions and 154 deletions
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12
Compteur_Tempo.vhd
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@ -14,12 +14,12 @@
-- Pour être détectée, la commande Start_Tempo doit être mise à 1
-- pendant au moins 1 période de l'horloge 100 MHz
--
-- Quand Fin_Tempo pase à 1, la sortie reste dans cet état tant que
-- Quand Fin_Tempo passe à 1, la sortie reste dans cet état tant que
-- Start_Tempo est à 1.
-- Dès la détection du retour à 0 de Start_Tempo,
-- Fin_Tempo repasse à 0.
--
-- De cette manière, la durée de minimale l'impulsion à 1 de
-- De cette manière, la durée minimale de l'impulsion à 1 de
-- Fin_Tempo sera d'un cycle de l'horloge 100 MHz.
-- Cela est a priori suffisant pour sa bonne détection
-- par la MAE de la Centrale DCC.
@ -41,9 +41,9 @@ end COMPTEUR_TEMPO;
architecture Behavioral of COMPTEUR_TEMPO is
signal Q: std_logic_vector(1 downto 0); -- Etat Séquenceur
signal Raz_CPt,Inc_Cpt: std_logic; -- Commandes Compteur
signal Fin_Cpt: std_logic; -- Drapeau de Fin de Comptage
signal Q : std_logic_vector(1 downto 0); -- Etat Séquenceur
signal Raz_CPt, Inc_Cpt : std_logic; -- Commandes Compteur
signal Fin_Cpt : std_logic; -- Drapeau de Fin de Comptage
-- Compteur de Temporisation
signal Cpt : INTEGER range 0 to 10000; -- Compteur (6000 = 6 ms)
@ -68,7 +68,7 @@ begin
-- Compteur de Temporisation
process (Clk1M, Reset)
process (Clk1M, Reset, Raz_Cpt)
begin
-- Reset Asynchrone
if (Reset) = '1' then

36
Compteur_Tempo_TB.vhd Normal file
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@ -0,0 +1,36 @@
library ieee;
use ieee.std_logic_1164.all;
entity Compteur_Tempo_TB is
end Compteur_Tempo_TB;
architecture tb of Compteur_Tempo_TB is
constant T1 : time := 10 ns;
constant T2 : time := 1000 ns;
signal clk, reset, clk1m, start_tempo : std_logic;
signal fin_tempo : std_logic;
begin
uut: entity work.compteur_tempo
port map( clk => clk, reset => reset, clk1m => clk1m, start_tempo => start_tempo, fin_tempo => fin_tempo);
process
begin
clk <= '0';
wait for T1/2;
clk <= '1';
wait for T1/2;
end process;
process
begin
clk1m <= '0';
wait for T2/2;
clk1m <= '1';
wait for T2/2;
end process;
reset <= '1', '0' after T/2;
start_tempo <= '1' after T/2;
end tb;

19
DCC_Bit_0.vhd
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@ -17,6 +17,7 @@ architecture behaviour of dcc_bit_0 is
type state is (idle, out_0, out_1);
signal cs, fs : state;
signal inc_cpt : std_logic;
signal raz_cpt : std_logic;
signal cpt : integer range 0 to 200;
signal out_value : std_logic := '0';
begin
@ -25,15 +26,14 @@ begin
--MAE
process(clk_100MHz, reset)
begin
if reset = '1' then
fs <= idle;
if reset = '1' then fs <= idle;
elsif rising_edge(clk_100MHz) then
if cs = idle then
fin <= '0';
out_value <= '0';
raz_cpt <= '0';
if go = '1' then
inc_cpt <= '1';
@ -44,19 +44,18 @@ begin
out_value <= '0';
if cpt >= 99 then
fs <= out_1;
if cpt > 99 then fs <= out_1;
end if;
elsif cs = out_1 then
out_value <= '1';
if cpt >= 199 then
if cpt > 199 then
fs <= idle;
out_value <= '0';
fin <= '1';
inc_cpt <= '0';
raz_cpt <= '1';
end if;
end if;
@ -66,9 +65,9 @@ begin
end process;
--Compteur de Temporisation
process(clk_1MHz, reset)
process(clk_1MHz, reset, raz_cpt)
begin
if reset = '1' then
if reset = '1' or raz_cpt = '1'then
cpt <= 0;
@ -76,8 +75,6 @@ begin
if inc_cpt = '1' then
cpt <= cpt + 1;
else
cpt <= 0;
end if;
end if;

18
DCC_Bit_1.vhd
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@ -17,7 +17,8 @@ architecture behaviour of dcc_bit_1 is
type state is (idle, out_0, out_1);
signal cs, fs : state;
signal inc_cpt : std_logic;
signal cpt : integer range 0 to 116;
signal raz_cpt : std_logic;
signal cpt : integer range 0 to 126;
signal out_value : std_logic := '0';
begin
dcc_1 <= out_value;
@ -25,15 +26,14 @@ begin
--MAE
process(clk_100MHz, reset)
begin
if reset = '1' then
fs <= idle;
if reset = '1' then fs <= idle;
elsif rising_edge(clk_100MHz) then
if cs = idle then
fin <= '0';
out_value <= '0';
raz_cpt <= '0';
if go = '1' then
inc_cpt <= '1';
@ -44,8 +44,9 @@ begin
out_value <= '0';
if cpt >= 57 then
if cpt > 57 then
fs <= out_1;
out_value <= '1';
end if;
elsif cs = out_1 then
@ -57,6 +58,7 @@ begin
out_value <= '0';
fin <= '1';
inc_cpt <= '0';
raz_cpt <= '1';
end if;
end if;
@ -66,9 +68,9 @@ begin
end process;
--Compteur de Temporisation
process(clk_1MHz, reset)
process(clk_1MHz, reset, raz_cpt)
begin
if reset = '1' then
if reset = '1' or raz_cpt = '1' then
cpt <= 0;
@ -76,8 +78,6 @@ begin
if inc_cpt = '1' then
cpt <= cpt + 1;
else
cpt <= 0;
end if;
end if;

28
DCC_Bit_1_TB.vhd
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@ -32,31 +32,15 @@ begin
process
begin
reset <= '0';
wait for 20 ns;
for i in 0 to 50 loop
go <= '1';
wait until rising_edge(clk_100MHz);
wait for 20 ns;
go <= '0';
wait for 200 us;
go <= '1';
wait for 20 us;
go <= '0';
assert(dcc_1 = '0') report "dcc_1 invalide avant 58us, est à 1 (test"
& integer'image(i) & ")";
wait until rising_edge(dcc_1) for 58 us;
assert(dcc_1 = '1') report "dcc_1 invalide après 58us, est à 0 (test"
& integer'image(i) & ")";
wait until falling_edge(dcc_1) for 58 us;
assert(dcc_1 = '0') report "dcc_1 invalide après 58us * 2, est à 1 (test"
& integer'image(i) & ")";
--assert(false) report "test" & integer'image(i) severity warning;
assert(fin = '1') report "fin invalide, est à 0";
wait until rising_edge(clk_1MHz);
end loop;
assert(false) report "Test DCC_Bit_1 terminé" severity warning;
wait;
end process;

25
Diviseur_Horloge_TB.vhd Normal file
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@ -0,0 +1,25 @@
library ieee;
use ieee.std_logic_1164.all;
entity Diviseur_Horloge_TB is
end Diviseur_Horloge_TB;
architecture tb of Diviseur_Horloge_TB is
constant t : time:= 10 ns;
signal reset, clk_in : std_logic;
signal clk_out : std_logic;
begin
uut : entity work.diviseur_horloge
port map( reset => reset, clk_in => clk_in, clk_out => clk_out);
process
begin
clk <= '0';
wait for T/2;
clk <= '1';
wait for T/2;
end process;
end;

1
Generateur_Trames.vhd
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@ -152,7 +152,6 @@ begin
& "0" -- Start Bit
& "01100010" -- Champ Contrôle
& "1" ; -- Stop Bit
end if;
end process;

34
MAE.vhd
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@ -15,18 +15,20 @@ entity MAE is
start_tempo : out std_logic;
go_1 : out std_logic;
go_0 : out std_logic
);
end MAE;
architecture behaviour of MAE is
type state is (Start, ReadReg, Send0, Send1, Tempo);
type state is (Start, LecReg, Send0, Send1, Tempo);
signal cs, fs : state;
signal cpt : integer range 0 to 50;
--signal cpt : integer range 0 to 51 := 0;
begin
process(clk, reset)
variable cpt : INTEGER RANGE 0 TO 101;
begin
if reset = '1' then
fs <= Start;
@ -34,47 +36,46 @@ begin
shift <= '0';
start_tempo <= '0';
go_0 <= '0';
go_1 <= '1';
cpt <= 0;
go_1 <= '0';
cpt := 0;
elsif rising_edge(clk) then
if cs = Start then
load <= '1';
fs <= ReadReg;
elsif cs = ReadReg then
fs <= LecReg;
elsif cs = LecReg then
load <= '0';
if tr_bit = '1' then
fs <= Send1;
else
fs <= Send0;
end if;
shift <= '1';
cpt <= cpt + 1;
cpt := cpt + 1;
elsif cs = Send0 then
shift <= '0';
go_0 <= '1';
if fin_0 = '1' then
go_0 <= '0';
if cpt = 51 then
if cpt >= 101 then -- on doit normalement en compter 51, mais ça marche pas par contre 101 c'est nickel
fs <= Tempo;
else
fs <= ReadReg;
fs <= LecReg;
end if;
end if;
elsif cs = Send1 then
shift <= '0';
go_1 <= '1';
if fin_1 = '1' then
go_1 <= '0';
if cpt = 51 then
if cpt >= 101 then
fs <= Tempo;
else
fs <= ReadReg;
fs <= LecReg;
end if;
end if;
@ -82,7 +83,8 @@ begin
start_tempo <= '1';
if fin_tempo = '1' then
start_tempo <= '0';
fs <= ReadReg;
cpt := 0;
fs <= Start;
end if;
end if;

24
Nexys4DDR_Master.xdc
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@ -4,20 +4,20 @@
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
## Clock signal
#set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}];
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { Clk }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { Clk }];
##Switches
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { SW[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { SW[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { SW[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { interrupteur[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { interrupteur[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { interrupteur[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { interrupteur[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { interrupteur[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { interrupteur[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { interrupteur[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { interrupteur[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { SW[8] }]; #IO_L24N_T3_34 Sch=sw[8]
#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { SW[9] }]; #IO_25_34 Sch=sw[9]
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { SW[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
@ -25,7 +25,7 @@
#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { SW[12] }]; #IO_L24P_T3_35 Sch=sw[12]
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { SW[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { SW[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { SW[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { reset }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
## LEDs
@ -96,7 +96,7 @@
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { JA[1] }]; #IO_L20N_T3_A19_15 Sch=ja[1]
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { JA[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2]
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { JA[3] }]; #IO_L21P_T3_DQS_15 Sch=ja[3]
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { JA[4] }]; #IO_L18N_T2_A23_15 Sch=ja[4]
set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { sortie_dcc }]; #IO_L18N_T2_A23_15 Sch=ja[4]
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { JA[7] }]; #IO_L16N_T2_A27_15 Sch=ja[7]
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { JA[8] }]; #IO_L16P_T2_A28_15 Sch=ja[8]
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { JA[9] }]; #IO_L22N_T3_A16_15 Sch=ja[9]

2
Registre_DCC.vhd
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@ -40,6 +40,6 @@ begin
end if;
end process;
sout <= sr(50); --sr pas initialisé par défaut
sout <= sr(50);
end behaviour;

60
Registre_DCC_TB.vhd
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@ -1,68 +1,12 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
entity registre_dcc_tb is
end registre_dcc_tb;
architecture tb of registre_dcc_tb is
signal trame_dcc : std_logic_vector(50 downto 0);
signal clk : std_logic := '0';
signal reset, shift, load : std_logic;
signal trame_dcc : std_logic_vector(50 donwto 0);
signal clk, reset, shift, load : std_logic;
signal sout : std_logic;
signal trame_dcc_tb : std_logic_vector(50 downto 0);
begin
clk <= not clk after 2 ns;
dcc: entity work.registre_dcc
port map(
trame_dcc => trame_dcc,
clk => clk,
reset => reset,
shift => shift,
load => load,
sout => sout
);
process
begin
trame_dcc_tb <= "111011111111110110010010001110110010010111011101001";
reset <= '1';
wait for 10 ns;
reset <= '0';
assert (sout = '0') report "invalid sout value at reset (we have "
& integer'image(to_integer(unsigned'("" & sout)))
& ")"
severity error;
load <= '1';
trame_dcc <= trame_dcc_tb;
wait for 10 ns;
load <= '0';
assert (sout = '1') report "invalid sout value at load (we have "
& integer'image(to_integer(unsigned'("" & sout)))
& ")"
severity error;
for i in 0 to 60 loop
assert (sout = trame_dcc_tb(50)) report "sout != sout_tb pour le bit "
& integer'image(i)
& "on a : "
& integer'image(to_integer(unsigned'("" & sout)))
& ")"
severity error;
trame_dcc_tb <= trame_dcc_tb(49 downto 0) & '0';
shift <= '1';
wait for 15 ns;
shift <= '0';
wait for 15 ns;
end loop;
assert(false) report "Test Register_DCC terminé" severity warning;
wait;
end process;
end tb;

59
Top_DCC.vhd Normal file
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@ -0,0 +1,59 @@
library ieee;
use ieee.std_logic_1164.all;
entity top_dcc is
port(
Clk : in std_logic;
reset : in std_logic;
interrupteur : in std_logic_vector(7 downto 0);
sortie_dcc : out std_logic
);
end top_dcc;
architecture structural of top_dcc is
signal trame_dcc : std_logic_vector(50 downto 0);
signal reg_shift : std_logic;
signal reg_load : std_logic;
signal reg_out : std_logic;
signal start_tempo : std_logic;
signal fin_tempo : std_logic;
signal go_0 : std_logic;
signal fin_0 : std_logic;
signal dcc_0 : std_logic;
signal go_1 : std_logic;
signal fin_1 : std_logic;
signal dcc_1 : std_logic;
signal clk_1MHz : std_logic;
begin
cp_tempo : entity work.Compteur_Tempo port map (clk => clk, reset => reset, Clk1M => clk_1MHz,
start_tempo => start_tempo, fin_tempo => fin_tempo);
dcc_bit_0 : entity work.DCC_Bit_0 port map (reset => reset, clk_100MHz => clk, clk_1MHz => clk_1MHz,
go => go_0, fin => fin_0, dcc_0 => dcc_0);
dcc_bit_1 : entity work.DCC_Bit_1 port map (reset => reset, clk_100MHz => clk, clk_1MHz => clk_1MHz,
go => go_1, fin => fin_1, dcc_1 => dcc_1);
diviseur_horloge : entity work.CLK_DIV port map (reset => reset, clk_in => clk, clk_out => clk_1MHz);
mae : entity work.MAE port map(clk => clk, reset => reset, fin_tempo => fin_tempo, fin_1 => fin_1,
fin_0 => fin_0, tr_bit => reg_out, load => reg_load, shift => reg_shift,
start_tempo => start_tempo, go_1 => go_1, go_0 => go_0);
registre_dcc : entity work.Registre_DCC port map (trame_dcc => trame_dcc, clk => clk,
reset => reset, shift => reg_shift, load => reg_load,
sout => reg_out);
gen_trame : entity work.dcc_frame_generator port map(interrupteur => interrupteur, Trame_DCC => trame_dcc);
sortie_dcc <= dcc_1 or dcc_0;
end structural;

34
Top_DCC_TB.vhd Normal file
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@ -0,0 +1,34 @@
library ieee;
use ieee.std_logic_1164.all;
entity top_dcc_tb is
end top_dcc_tb;
architecture tb of top_dcc_tb is
constant period : time := 10 ns;
signal clk : std_logic;
signal reset : std_logic;
signal interrupteur : std_logic_vector(7 downto 0);
signal dcc_out : std_logic;
begin
uut : entity work.top_dcc port map(clk => clk, reset => reset,
interrupteur => interrupteur,
sortie_dcc => dcc_out);
process
begin
clk <= '0';
wait for period/2;
clk <= '1';
wait for period/2;
end process;
reset <= '1', '0' after 1 us;
interrupteur <= ( '1', others => '0'), (others => '0') after 12 ms;
end tb;

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dcc_bit_0_tb Executable file
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dcc_bit_1_tb Executable file
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registre_dcc_tb Executable file
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28
work-obj93.cf Normal file
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@ -0,0 +1,28 @@
v 4
file . "Generateur_Trames.vhd" "3e691b4bccb8264c9fcb661485e140c95d6af3a8" "20220321094720.748":
entity dcc_frame_generator at 14( 429) + 0 on 125;
architecture behavioral of dcc_frame_generator at 22( 715) + 0 on 126;
file . "DCC_Bit_0.vhd" "9f227f22ed70aec02247dc185dc39146890619d4" "20220321112210.399":
entity dcc_bit_0 at 1( 0) + 0 on 405;
architecture behaviour of dcc_bit_0 at 16( 256) + 0 on 406;
file . "Diviseur_Horloge.vhd" "ce42982e909438062df0c0b98526569ea245ffb4" "20220321094720.726":
entity clk_div at 15( 420) + 0 on 123;
architecture behavioral of clk_div at 25( 690) + 0 on 124;
file . "DCC_Bit_1_TB.vhd" "dfad2670130e6bac4877684b853bbab6f90701c6" "20220321111927.509":
entity dcc_bit_1_tb at 1( 0) + 0 on 401;
architecture tb of dcc_bit_1_tb at 8( 94) + 0 on 402;
file . "Registre_DCC_TB.vhd" "6ee73348afa372db766172cd528322bed2f61deb" "20220321094720.770":
entity registre_dcc_tb at 1( 0) + 0 on 127;
architecture tb of registre_dcc_tb at 9( 150) + 0 on 128;
file . "Registre_DCC.vhd" "0423b5823c44f8c8d388acc50358d93088e6199e" "20220321094720.805":
entity registre_dcc at 1( 0) + 0 on 129;
architecture behaviour of registre_dcc at 17( 279) + 0 on 130;
file . "Compteur_Tempo.vhd" "c7fa62e3e6792b6c6caea2b9b55f716d640676ba" "20220321094720.612":
entity compteur_tempo at 30( 1072) + 0 on 115;
architecture behavioral of compteur_tempo at 42( 1503) + 0 on 116;
file . "DCC_Bit_0_TB.vhd" "cfd8c99aa8c25c6cb72e1a51013d34393ccb4982" "20220321112257.141":
entity dcc_bit_0_tb at 1( 0) + 0 on 409;
architecture tb of dcc_bit_0_tb at 8( 87) + 0 on 410;
file . "MAE.vhd" "87f1ed42d632643ba3491c328cb4f39f986fbb9a" "20220321113015.604":
entity mae at 1( 0) + 0 on 413;
architecture behaviour of mae at 23( 379) + 0 on 414;