DCC_Bit_0_TB.vhd

DCC_Bit_0_TB.vhd

@@ -0,0 +1,63 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dcc_bit_0_tb is
+end dcc_bit_0_tb;
+
+
+architecture tb of dcc_bit_0_tb is
+
+	constant ClockPeriod1 : time := 1 us;
+	constant ClockPeriod100 : time := 10 ns;
+
+	signal reset : std_logic := '1';
+	signal go : std_logic :=  '0'; --inputs
+	signal clk_100MHz : std_logic := '0';
+	signal clk_1MHz : std_logic := '0'; --clocks
+	signal fin, dcc_0 : std_logic; --outputs
+
+begin
+	uut : entity work.DCC_Bit_0 port map(
+						reset => reset,
+						clk_100MHz => clk_100Mhz,
+						clk_1MHz => clk_1MHz,
+						go => go,
+						fin => fin,
+						dcc_0 => dcc_0
+					);
+
+	clk_100MHz <= not clk_100MHz after ClockPeriod100 / 2;
+	clk_1MHz <= not clk_1MHz after ClockPeriod1 / 2;
+	
+	process
+	begin
+		reset <= '0';
+		wait for 20 ns;
+		
+		for i in 0 to 50 loop
+			go <= '1';
+			wait until rising_edge(clk_100MHz);
+			go <= '0';
+
+			assert(dcc_0 = '0') report "dcc_0 invalide avant 58us, est à 1 (test" 
+				& integer'image(i) & ")";
+			wait until rising_edge(dcc_0) for 100 us;
+			assert(dcc_0 = '1') report "dcc_0 invalide après 58us, est à 0 (test"
+				& integer'image(i) & ")";
+			wait until falling_edge(dcc_0) for 100 us;
+			assert(dcc_0 = '0') report "dcc_0 invalide après 58us * 2, est à 1 (test"
+				& integer'image(i) & ")";
+
+			--assert(false) report "test" & integer'image(i) severity warning;
+			assert(fin = '1') report "fin invalide, est à 0";
+			
+			wait until rising_edge(clk_1MHz);
+
+		end loop;
+		
+		assert(false) report "Test DCC_Bit_0 terminé" severity warning;
+		
+		wait;
+	end process;
+	
+end tb;