34 lines
793 B
VHDL
34 lines
793 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity top_dcc_tb is
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end top_dcc_tb;
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architecture tb of top_dcc_tb is
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constant period : time := 10 ns;
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signal clk : std_logic;
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signal reset : std_logic;
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signal interrupteur : std_logic_vector(7 downto 0);
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signal dcc_out : std_logic;
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begin
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uut : entity work.top_dcc port map(clk => clk, reset => reset,
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interrupteur => interrupteur,
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sortie_dcc => dcc_out);
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process
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begin
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clk <= '0';
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wait for period/2;
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clk <= '1';
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wait for period/2;
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end process;
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reset <= '1', '0' after 1 us;
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interrupteur <= ( '1', others => '0'), (others => '0') after 12 ms;
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end tb; |