Générateur trames et bit_0,1_dcc code ok
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library ieee;
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use ieee.std_logic_1164.all;
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entity dcc_bit_0 is
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port(
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reset : in std_logic;
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clk_100MHz : in std_logic;
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clk_1MHz : in std_logic;
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go : in std_logic;
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fin : out std_logic;
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dcc_0 : out std_logic
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);
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end dcc_bit_0;
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architecture behaviour of dcc_bit_0 is
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type state is (idle, out_0, out_1);
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signal cs, fs : state;
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signal inc_cpt : std_logic;
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signal cpt : integer range 0 to 200;
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signal out_value : std_logic := '0';
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begin
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dcc_0 <= out_value;
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--MAE
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process(clk_100MHz, reset)
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begin
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if reset = '1' then fs <= idle;
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elsif rising_edge(clk_100MHz) then
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if cs = idle then
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fin <= '0';
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out_value <= '0';
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if go = '1' then
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inc_cpt <= '1';
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fs <= out_0;
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end if;
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elsif cs = out_0 then
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out_value <= '0';
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if cpt > 99 then fs <= out_1;
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end if;
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elsif cs = out_1 then
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out_value <= '1';
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if cpt > 199 then
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fs <= idle;
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fin <= '1';
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inc_cpt <= '0';
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end if;
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end if;
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cs <= fs;
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end if;
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end process;
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--Compteur de Temporisation
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process(clk_1MHz, reset)
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begin
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if reset = '1' then
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cpt <= 0;
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elsif rising_edge(clk_1MHz) then
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if inc_cpt = '1' then
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cpt <= cpt + 1;
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end if;
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end if;
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end process;
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end behaviour;
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@ -0,0 +1,81 @@
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library ieee;
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use ieee.std_logic_1164.all;
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entity dcc_bit_1 is
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port(
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reset : in std_logic;
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clk_100MHz : in std_logic;
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clk_1MHz : in std_logic;
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go : in std_logic;
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fin : out std_logic;
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dcc_1 : out std_logic
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);
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end dcc_bit_1;
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architecture behaviour of dcc_bit_1 is
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type state is (idle, out_0, out_1);
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signal cs, fs : state;
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signal inc_cpt : std_logic;
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signal cpt : integer range 0 to 126;
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signal out_value : std_logic := '0';
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begin
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dcc_1 <= out_value;
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--MAE
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process(clk_100MHz, reset)
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begin
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if reset = '1' then fs <= idle;
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elsif rising_edge(clk_100MHz) then
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if cs = idle then
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fin <= '0';
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out_value <= '0';
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if go = '1' then
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inc_cpt <= '1';
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fs <= out_0;
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end if;
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elsif cs = out_0 then
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out_value <= '0';
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if cpt > 57 then fs <= out_1;
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end if;
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elsif cs = out_1 then
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out_value <= '1';
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if cpt > 125 then
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fs <= idle;
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fin <= '1';
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inc_cpt <= '0';
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end if;
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end if;
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cs <= fs;
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end if;
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end process;
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--Compteur de Temporisation
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process(clk_1MHz, reset)
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begin
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if reset = '1' then
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cpt <= 0;
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elsif rising_edge(clk_1MHz) then
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if inc_cpt = '1' then
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cpt <= cpt + 1;
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end if;
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end if;
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end process;
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end behaviour;
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@ -0,0 +1,43 @@
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library ieee;
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use ieee.std_logic_1164.all;
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entity dcc_bit_1_tb is
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end dcc_bit_1_tb;
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architecture tb of dcc_bit_1_tb is
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constant ClockPeriod1 : time := 1 us;
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constant ClockPeriod100 : time := 10 ns;
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signal reset : std_logic := '1';
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signal go : std_logic := '0'; --inputs
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signal clk_100MHz : std_logic := '0';
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signal clk_1MHz : std_logic := '0'; --clocks
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signal fin, dcc_1 : std_logic; --outputs
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begin
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uut : entity work.DCC_Bit_1 port map(
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reset => reset,
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clk_100MHz => clk_100Mhz,
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clk_1MHz => clk_1MHz,
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go => go,
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fin => fin,
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dcc_1 => dcc_1
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);
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clk_100MHz <= not clk_100MHz after ClockPeriod100 / 2;
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clk_1MHz <= not clk_1MHz after ClockPeriod1 / 2;
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process
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begin
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reset <= '0';
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wait for 20 ns;
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go <= '1';
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wait for 30 ns;
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go <= '0';
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wait;
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end process;
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end tb;
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@ -35,7 +35,7 @@ begin
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--> Trame Marche Avant du Train d'Adresse i
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if Interrupteur(7)='1' then
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Trame_DCC <= "1111111111111111111111" -- Préambule
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Trame_DCC <= "11111111111111111111111" -- Préambule
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& "0" -- Start Bit
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& "00000010" -- Champ Adresse (adresse 2 sans raison particuliere )
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& "0" -- Start Bit
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@ -48,7 +48,7 @@ begin
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--> Trame Marche Arrière du Train d'Adresse i
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elsif Interrupteur(6)='1' then
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Trame_DCC <= "1111111111111111111111" -- Préambule
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Trame_DCC <= "11111111111111111111111" -- Préambule
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& "0" -- Start Bit
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& "00000010" -- Champ Adresse
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& "0" -- Start Bit
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@ -62,7 +62,7 @@ begin
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--> Allumage des Phares du Train d'Adresse i
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elsif Interrupteur(5)='1' then
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Trame_DCC <= "1111111111111111111111" -- Préambule
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Trame_DCC <= "11111111111111111111111" -- Préambule
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& "0" -- Start Bit
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& "00000010" -- Champ Adresse
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& "0" -- Start Bit
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@ -75,7 +75,7 @@ begin
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--> Extinction des Phares du Train d'Adresse i
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elsif Interrupteur(4)='1' then
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Trame_DCC <= "1111111111111111111111" -- Préambule
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Trame_DCC <= "11111111111111111111111" -- Préambule
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& "0" -- Start Bit
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& "00000010" -- Champ Adresse
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& "0" -- Start Bit
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@ -88,7 +88,7 @@ begin
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--> Activation du Klaxon (Fonction F11) du Train d'Adresse i
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elsif Interrupteur(3)='1' then
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Trame_DCC <= "1111111111111111111111" -- Préambule
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Trame_DCC <= "11111111111111111111111" -- Préambule
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& "0" -- Start Bit
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& "00000010" -- Champ Adresse
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& "0" -- Start Bit
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@ -101,7 +101,7 @@ begin
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--> Réamorçage du Klaxon (Fonction F11) du Train d'Adresse i
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elsif Interrupteur(2)='1' then
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Trame_DCC <= "1111111111111111111111" -- Préambule
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Trame_DCC <= "11111111111111111111111" -- Préambule
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& "0" -- Start Bit
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& "00000010" -- Champ Adresse
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& "0" -- Start Bit
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@ -144,7 +144,7 @@ begin
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--> Arrêt du Train d'Adresse i
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else
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Trame_DCC <= "1111111111111111111111" -- Préambule
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Trame_DCC <= "11111111111111111111111" -- Préambule
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& "0" -- Start Bit
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& "00000010" -- Champ Adresse
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& "0" -- Start Bit
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@ -153,6 +153,8 @@ begin
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& "01100010" -- Champ Contrôle
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& "1" ; -- Stop Bit
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end if;
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end process;
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end Behavioral;
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