From 0b57bc498781a87c41e64c5aaf1ac16d7d21c7a9 Mon Sep 17 00:00:00 2001 From: Adrien Bourmault Date: Mon, 21 Mar 2022 10:47:55 +0100 Subject: [PATCH] =?UTF-8?q?G=C3=A9n=C3=A9rateur=20trames=20et=20bit=5F0,1?= =?UTF-8?q?=5Fdcc=20code=20ok?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- DCC_Bit_0.vhd | 81 +++++++++++++++++++++++++++++++++++++++++++ DCC_Bit_1.vhd | 81 +++++++++++++++++++++++++++++++++++++++++++ DCC_Bit_1_TB.vhd | 43 +++++++++++++++++++++++ Generateur_Trames.vhd | 16 +++++---- 4 files changed, 214 insertions(+), 7 deletions(-) create mode 100644 DCC_Bit_0.vhd create mode 100644 DCC_Bit_1.vhd create mode 100644 DCC_Bit_1_TB.vhd diff --git a/DCC_Bit_0.vhd b/DCC_Bit_0.vhd new file mode 100644 index 0000000..02786fa --- /dev/null +++ b/DCC_Bit_0.vhd @@ -0,0 +1,81 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity dcc_bit_0 is + port( + reset : in std_logic; + clk_100MHz : in std_logic; + clk_1MHz : in std_logic; + go : in std_logic; + fin : out std_logic; + dcc_0 : out std_logic + ); +end dcc_bit_0; + + +architecture behaviour of dcc_bit_0 is + type state is (idle, out_0, out_1); + signal cs, fs : state; + signal inc_cpt : std_logic; + signal cpt : integer range 0 to 200; + signal out_value : std_logic := '0'; +begin + dcc_0 <= out_value; + + --MAE + process(clk_100MHz, reset) + begin + if reset = '1' then fs <= idle; + elsif rising_edge(clk_100MHz) then + + if cs = idle then + + fin <= '0'; + out_value <= '0'; + + if go = '1' then + inc_cpt <= '1'; + fs <= out_0; + end if; + + elsif cs = out_0 then + + out_value <= '0'; + + if cpt > 99 then fs <= out_1; + end if; + + elsif cs = out_1 then + + out_value <= '1'; + + if cpt > 199 then + fs <= idle; + fin <= '1'; + inc_cpt <= '0'; + end if; + + end if; + cs <= fs; + end if; + + end process; + + --Compteur de Temporisation + process(clk_1MHz, reset) + begin + if reset = '1' then + + cpt <= 0; + + elsif rising_edge(clk_1MHz) then + + if inc_cpt = '1' then + cpt <= cpt + 1; + end if; + + end if; + end process; + + +end behaviour; diff --git a/DCC_Bit_1.vhd b/DCC_Bit_1.vhd new file mode 100644 index 0000000..b87461f --- /dev/null +++ b/DCC_Bit_1.vhd @@ -0,0 +1,81 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity dcc_bit_1 is + port( + reset : in std_logic; + clk_100MHz : in std_logic; + clk_1MHz : in std_logic; + go : in std_logic; + fin : out std_logic; + dcc_1 : out std_logic + ); +end dcc_bit_1; + + +architecture behaviour of dcc_bit_1 is + type state is (idle, out_0, out_1); + signal cs, fs : state; + signal inc_cpt : std_logic; + signal cpt : integer range 0 to 126; + signal out_value : std_logic := '0'; +begin + dcc_1 <= out_value; + + --MAE + process(clk_100MHz, reset) + begin + if reset = '1' then fs <= idle; + elsif rising_edge(clk_100MHz) then + + if cs = idle then + + fin <= '0'; + out_value <= '0'; + + if go = '1' then + inc_cpt <= '1'; + fs <= out_0; + end if; + + elsif cs = out_0 then + + out_value <= '0'; + + if cpt > 57 then fs <= out_1; + end if; + + elsif cs = out_1 then + + out_value <= '1'; + + if cpt > 125 then + fs <= idle; + fin <= '1'; + inc_cpt <= '0'; + end if; + + end if; + cs <= fs; + end if; + + end process; + + --Compteur de Temporisation + process(clk_1MHz, reset) + begin + if reset = '1' then + + cpt <= 0; + + elsif rising_edge(clk_1MHz) then + + if inc_cpt = '1' then + cpt <= cpt + 1; + end if; + + end if; + end process; + + +end behaviour; \ No newline at end of file diff --git a/DCC_Bit_1_TB.vhd b/DCC_Bit_1_TB.vhd new file mode 100644 index 0000000..ad772a4 --- /dev/null +++ b/DCC_Bit_1_TB.vhd @@ -0,0 +1,43 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity dcc_bit_1_tb is +end dcc_bit_1_tb; + + +architecture tb of dcc_bit_1_tb is + + constant ClockPeriod1 : time := 1 us; + constant ClockPeriod100 : time := 10 ns; + + signal reset : std_logic := '1'; + signal go : std_logic := '0'; --inputs + signal clk_100MHz : std_logic := '0'; + signal clk_1MHz : std_logic := '0'; --clocks + signal fin, dcc_1 : std_logic; --outputs + +begin + uut : entity work.DCC_Bit_1 port map( + reset => reset, + clk_100MHz => clk_100Mhz, + clk_1MHz => clk_1MHz, + go => go, + fin => fin, + dcc_1 => dcc_1 + ); + + clk_100MHz <= not clk_100MHz after ClockPeriod100 / 2; + clk_1MHz <= not clk_1MHz after ClockPeriod1 / 2; + + process + begin + reset <= '0'; + + wait for 20 ns; + go <= '1'; + wait for 30 ns; + go <= '0'; + wait; + end process; + +end tb; \ No newline at end of file diff --git a/Generateur_Trames.vhd b/Generateur_Trames.vhd index f06aaf0..e8e21f5 100644 --- a/Generateur_Trames.vhd +++ b/Generateur_Trames.vhd @@ -35,7 +35,7 @@ begin --> Trame Marche Avant du Train d'Adresse i if Interrupteur(7)='1' then - Trame_DCC <= "1111111111111111111111" -- Préambule + Trame_DCC <= "11111111111111111111111" -- Préambule & "0" -- Start Bit & "00000010" -- Champ Adresse (adresse 2 sans raison particuliere ) & "0" -- Start Bit @@ -48,7 +48,7 @@ begin --> Trame Marche Arrière du Train d'Adresse i elsif Interrupteur(6)='1' then - Trame_DCC <= "1111111111111111111111" -- Préambule + Trame_DCC <= "11111111111111111111111" -- Préambule & "0" -- Start Bit & "00000010" -- Champ Adresse & "0" -- Start Bit @@ -62,7 +62,7 @@ begin --> Allumage des Phares du Train d'Adresse i elsif Interrupteur(5)='1' then - Trame_DCC <= "1111111111111111111111" -- Préambule + Trame_DCC <= "11111111111111111111111" -- Préambule & "0" -- Start Bit & "00000010" -- Champ Adresse & "0" -- Start Bit @@ -75,7 +75,7 @@ begin --> Extinction des Phares du Train d'Adresse i elsif Interrupteur(4)='1' then - Trame_DCC <= "1111111111111111111111" -- Préambule + Trame_DCC <= "11111111111111111111111" -- Préambule & "0" -- Start Bit & "00000010" -- Champ Adresse & "0" -- Start Bit @@ -88,7 +88,7 @@ begin --> Activation du Klaxon (Fonction F11) du Train d'Adresse i elsif Interrupteur(3)='1' then - Trame_DCC <= "1111111111111111111111" -- Préambule + Trame_DCC <= "11111111111111111111111" -- Préambule & "0" -- Start Bit & "00000010" -- Champ Adresse & "0" -- Start Bit @@ -101,7 +101,7 @@ begin --> Réamorçage du Klaxon (Fonction F11) du Train d'Adresse i elsif Interrupteur(2)='1' then - Trame_DCC <= "1111111111111111111111" -- Préambule + Trame_DCC <= "11111111111111111111111" -- Préambule & "0" -- Start Bit & "00000010" -- Champ Adresse & "0" -- Start Bit @@ -144,7 +144,7 @@ begin --> Arrêt du Train d'Adresse i else - Trame_DCC <= "1111111111111111111111" -- Préambule + Trame_DCC <= "11111111111111111111111" -- Préambule & "0" -- Start Bit & "00000010" -- Champ Adresse & "0" -- Start Bit @@ -153,6 +153,8 @@ begin & "01100010" -- Champ Contrôle & "1" ; -- Stop Bit + end if; + end process; end Behavioral;