50 lines
1.4 KiB
VHDL
50 lines
1.4 KiB
VHDL
library ieee;
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use ieee.math_real.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_1164.all;
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entity shifter_tb is
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end shifter_tb;
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ARCHITECTURE Structurel OF Shifter_tb is
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signal shift_lsl : Std_Logic := '0';
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signal shift_lsr : Std_Logic := '0';
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signal shift_asr : Std_Logic := '0';
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signal shift_ror : Std_Logic := '0';
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signal shift_rrx : Std_Logic := '0';
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signal shift_val : Std_Logic_Vector(4 downto 0);
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signal din : Std_Logic_Vector(31 downto 0);
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signal cin : Std_Logic := '0';
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signal dout : Std_Logic_Vector(31 downto 0);
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signal cout : Std_Logic;
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signal vdd : bit := '1';
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signal vss : bit := '0';
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begin
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shift: entity work.Shifter
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port map(
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shift_lsl => shift_lsl,
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shift_lsr => shift_lsr,
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shift_asr => shift_asr,
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shift_ror => shift_ror,
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shift_rrx => shift_rrx,
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shift_val => shift_val,
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din => din,
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cin => cin,
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dout => dout,
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cout => cout,
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vdd => vdd,
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vss => vss
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);
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process
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begin
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shift_ror <= '1';
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shift_val <= "00010";
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din <= std_logic_vector(to_unsigned(32654, 32));
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wait for 5 ns;
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report "dout = " & integer'image(to_integer(unsigned(dout)));
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WAIT;
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end process;
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end Structurel;
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