72 lines
1.2 KiB
VHDL
72 lines
1.2 KiB
VHDL
LIBRARY ieee;
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use ieee.std_logic_1164.all;
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ENTITY fifo IS
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PORT(
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din : in std_logic_vector(71 downto 0);
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dout : out std_logic_vector(71 downto 0);
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-- commands
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push : in std_logic;
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pop : in std_logic;
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-- flags
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full : out std_logic;
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empty : out std_logic;
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reset_n : in std_logic;
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ck : in std_logic;
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vdd : in bit;
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vss : in bit
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);
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END fifo;
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architecture dataflow of fifo is
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signal fifo_d : std_logic_vector(71 downto 0);
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signal fifo_v : std_logic;
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begin
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process(ck)
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begin
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if rising_edge(ck) then
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-- Valid bit
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if reset_n = '0' then
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fifo_v <= '0';
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else
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if fifo_v = '0' then
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if push = '1' then
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fifo_v <= '1';
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else
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fifo_v <= '0';
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end if;
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else
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if pop = '1' then
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if push = '1' then
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fifo_v <= '1';
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else
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fifo_v <= '0';
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end if;
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else
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fifo_v <= '1';
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end if;
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end if;
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end if;
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-- data
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if fifo_v = '0' then
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if push = '1' then
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fifo_d <= din;
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end if;
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elsif push='1' and pop='1' then
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fifo_d <= din;
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end if;
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end if;
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end process;
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full <= '1' when fifo_v = '1' and pop = '0' else '0';
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empty <= not fifo_v;
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dout <= fifo_d;
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end dataflow; |