Clean

shifter.vcd

@@ -1,62 +0,0 @@
-$date
-  Wed Oct 27 12:29:22 2021
-$end
-$version
-  GHDL v0
-$end
-$timescale
-  1 fs
-$end
-$var reg 1 ! shift_lsl $end
-$var reg 1 " shift_lsr $end
-$var reg 1 # shift_asr $end
-$var reg 1 $ shift_ror $end
-$var reg 1 % shift_rrx $end
-$var reg 5 & shift_val[4:0] $end
-$var reg 32 ' din[31:0] $end
-$var reg 1 ( cin $end
-$var reg 32 ) dout[31:0] $end
-$var reg 1 * cout $end
-$var reg 1 + vdd $end
-$var reg 1 , vss $end
-$scope module shift $end
-$var reg 1 - shift_lsl $end
-$var reg 1 . shift_lsr $end
-$var reg 1 / shift_asr $end
-$var reg 1 0 shift_ror $end
-$var reg 1 1 shift_rrx $end
-$var reg 5 2 shift_val[4:0] $end
-$var reg 32 3 din[31:0] $end
-$var reg 1 4 cin $end
-$var reg 32 5 dout[31:0] $end
-$var reg 1 6 cout $end
-$var reg 1 7 vdd $end
-$var reg 1 8 vss $end
-$upscope $end
-$enddefinitions $end
-#0
-0!
-0"
-0#
-1$
-0%
-b00010 &
-b00000000000000000111111110001110 '
-0(
-b10000000000000000001111111100011 )
-1*
-1+
-0,
-0-
-0.
-0/
-10
-01
-b00010 2
-b00000000000000000111111110001110 3
-04
-b10000000000000000001111111100011 5
-16
-17
-08
-#5000000

work-obj93.cf

@@ -1,7 +0,0 @@
-v 4
-file . "shifter_tb.vhdl" "91f07b86fce3e94d1a78f6ff81549324e4c127b6" "20211027102922.006":
-  entity shifter_tb at 1( 0) + 0 on 69;
-  architecture structurel of shifter_tb at 9( 132) + 0 on 70;
-file . "shifter.vhdl" "19ae95a81c4d07ea688fa5629b00a8ab21404624" "20211027101726.934":
-  entity shifter at 1( 0) + 0 on 53;
-  architecture shifter_bhvr of shifter at 33( 791) + 0 on 54;