parent
25f67ed707
commit
83229c5c85
2
Makefile
2
Makefile
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@ -1,5 +1,5 @@
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GHDL = ghdl
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all : sim_alu sim_shifter
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all : sim_alu #sim_shifter
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%.o : %.vhdl
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${GHDL} -a -g -v $^
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@ -3,10 +3,10 @@ use ieee.math_real.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_1164.all;
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entity ALU_tb is
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end ALU_tb;
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entity ALU is
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end ALU;
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architecture Structurel of ALU_tb is
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architecture Structurel of ALU is
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--! ######## signals for component ########
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@ -33,7 +33,7 @@ architecture Structurel of ALU_tb is
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end function;
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begin
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alu_0 : entity work.ALU
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alu_0 : entity work.alu
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port map(
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op1 => op1,
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op2 => op2,
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@ -39,7 +39,6 @@ architecture Shifter_bhvr of Shifter is
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begin
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temp_dout := din;
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temp_cout := cin;
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-- LSL -------------------------------------------------------------
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-- 1
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if(shift_lsl='1' and shift_val(0)='1')
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@ -39,8 +39,8 @@ port map(
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process
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begin
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shift_ror <= '1';
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shift_val <= "00100";
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din <= std_logic_vector(to_unsigned(4, 32));
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shift_val <= "00010";
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din <= std_logic_vector(to_unsigned(32654, 32));
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wait for 5 ns;
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report "dout = " & integer'image(to_integer(unsigned(dout)));
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WAIT;
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