Shifter tb
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c42e9315a5
commit
5375e88722
158
shifter_tb.vhdl
158
shifter_tb.vhdl
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@ -59,7 +59,9 @@ begin
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seed2 := 1;
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wait for 1 ns;
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report "[test_01] lsl with 32 random values";
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-- lsl
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report "lsl with 32 random values";
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shift_lsl <= '1';
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la : for va in 0 to 31 loop
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@ -79,21 +81,159 @@ begin
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end if;
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wait for 1 ns;
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--vdout := ?
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--vcout := ?
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vdout := din sll shift_val;
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vcout := 0;
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report "[test_01]: din = " & integer'image(to_integer(unsigned(din)));
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report "[test_01]: shift_val = " & integer'image(to_integer(unsigned(shift_val)));
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report "din = " & integer'image(to_integer(unsigned(din)));
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report "shift_val = " & integer'image(to_integer(unsigned(shift_val)));
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assert (dout = vdout) report "[error] lsl. vdout = " & integer'image(to_integer(unsigned(vdout))) & " versus dout = " & integer'image(to_integer(unsigned(dout))) severity error;
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assert (cout = vcout) report "[error] lsl. vcout = " & integer'image(to_integer(unsigned(vcout))) & " versus cout = " & integer'image(to_integer(unsigned(cout))) severity error;
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--assert (cout = vcout) report "[error] lsl. vcout = " & integer'image(to_integer(unsigned(vcout))) & " versus cout = " & integer'image(to_integer(unsigned(cout))) severity error;
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end loop la;
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report "[test_01] finished";
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wait for 1 ns;
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assert false report "end_of_test" severity note;
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-- wait forever; this will finish the simulation.
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-- lsr
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report "lsr with 32 random values";
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shift_lsl <= '0';
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shift_lsr <= '1';
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la : for va in 0 to 31 loop
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uniform(seed1, seed2, x);
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y := integer(floor(x * 31.0)) + 1;
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shift_val <= std_logic_vector(to_unsigned(y, shift_val'length));
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uniform(seed1, seed2, x);
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y := integer(floor(x * 536870911.0));
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din <= std_logic_vector(to_unsigned(y, din'length));
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if (y mod 2) = 0 then
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cin <= '1';
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else
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cin <= '0';
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end if;
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wait for 1 ns;
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vdout := din ror shift_val;
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vcout := 0;
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report "din = " & integer'image(to_integer(unsigned(din)));
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report "shift_val = " & integer'image(to_integer(unsigned(shift_val)));
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assert (dout = vdout) report "[error] lsl. vdout = " & integer'image(to_integer(unsigned(vdout))) & " versus dout = " & integer'image(to_integer(unsigned(dout))) severity error;
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--assert (cout = vcout) report "[error] lsl. vcout = " & integer'image(to_integer(unsigned(vcout))) & " versus cout = " & integer'image(to_integer(unsigned(cout))) severity error;
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end loop la;
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wait for 1 ns;
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-- asr
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report "asr with 32 random values";
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shift_asr <= '1';
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shift_lsr <= '0';
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la : for va in 0 to 31 loop
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uniform(seed1, seed2, x);
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y := integer(floor(x * 31.0)) + 1;
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shift_val <= std_logic_vector(to_unsigned(y, shift_val'length));
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uniform(seed1, seed2, x);
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y := integer(floor(x * 536870911.0));
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din <= std_logic_vector(to_unsigned(y, din'length));
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if (y mod 2) = 0 then
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cin <= '1';
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else
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cin <= '0';
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end if;
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wait for 1 ns;
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vdout := din sra shift_val;
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vcout := 0;
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report "din = " & integer'image(to_integer(unsigned(din)));
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report "shift_val = " & integer'image(to_integer(unsigned(shift_val)));
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assert (dout = vdout) report "[error] lsl. vdout = " & integer'image(to_integer(unsigned(vdout))) & " versus dout = " & integer'image(to_integer(unsigned(dout))) severity error;
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--assert (cout = vcout) report "[error] lsl. vcout = " & integer'image(to_integer(unsigned(vcout))) & " versus cout = " & integer'image(to_integer(unsigned(cout))) severity error;
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end loop la;
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wait for 1 ns;
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-- ror
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report "ror with 32 random values";
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shift_ror <= '1';
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shift_asr <= '0';
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la : for va in 0 to 31 loop
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uniform(seed1, seed2, x);
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y := integer(floor(x * 31.0)) + 1;
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shift_val <= std_logic_vector(to_unsigned(y, shift_val'length));
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uniform(seed1, seed2, x);
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y := integer(floor(x * 536870911.0));
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din <= std_logic_vector(to_unsigned(y, din'length));
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if (y mod 2) = 0 then
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cin <= '1';
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else
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cin <= '0';
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end if;
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wait for 1 ns;
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vdout := din ror shift_val;
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vcout := 0;
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report "din = " & integer'image(to_integer(unsigned(din)));
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report "shift_val = " & integer'image(to_integer(unsigned(shift_val)));
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assert (dout = vdout) report "[error] lsl. vdout = " & integer'image(to_integer(unsigned(vdout))) & " versus dout = " & integer'image(to_integer(unsigned(dout))) severity error;
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--assert (cout = vcout) report "[error] lsl. vcout = " & integer'image(to_integer(unsigned(vcout))) & " versus cout = " & integer'image(to_integer(unsigned(cout))) severity error;
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end loop la;
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wait for 1 ns;
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-- rrx
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report "rrx with 32 random values";
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shift_rrx <= '1';
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shift_ror <= '0';
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la : for va in 0 to 31 loop
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uniform(seed1, seed2, x);
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y := integer(floor(x * 31.0)) + 1;
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shift_val <= std_logic_vector(to_unsigned(y, shift_val'length));
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uniform(seed1, seed2, x);
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y := integer(floor(x * 536870911.0));
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din <= std_logic_vector(to_unsigned(y, din'length));
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if (y mod 2) = 0 then
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cin <= '1';
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else
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cin <= '0';
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end if;
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wait for 1 ns;
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vdout := din rrx shift_val;
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vcout := 0;
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report "din = " & integer'image(to_integer(unsigned(din)));
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report "shift_val = " & integer'image(to_integer(unsigned(shift_val)));
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--assert (dout = vdout) report "[error] lsl. vdout = " & integer'image(to_integer(unsigned(vdout))) & " versus dout = " & integer'image(to_integer(unsigned(dout))) severity error;
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--assert (cout = vcout) report "[error] lsl. vcout = " & integer'image(to_integer(unsigned(vcout))) & " versus cout = " & integer'image(to_integer(unsigned(cout))) severity error;
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end loop la;
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wait for 1 ns;
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wait;
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end process;
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