projet-vlsi/shifter_tb.vhdl

library ieee;
use ieee.math_real.all;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;

entity shifter_tb is
end shifter_tb;

ARCHITECTURE Structurel OF Shifter_tb is 
signal  shift_lsl :     Std_Logic := '0';
signal  shift_lsr :     Std_Logic := '0';    
signal  shift_asr :     Std_Logic := '0';
signal  shift_ror :     Std_Logic := '0';
signal  shift_rrx :     Std_Logic := '0';    
signal  shift_val :     Std_Logic_Vector(4 downto 0);
signal  din       :     Std_Logic_Vector(31 downto 0);
signal  cin       :     Std_Logic := '0';
signal  dout      :     Std_Logic_Vector(31 downto 0);
signal  cout      :     Std_Logic;
signal  vdd       :     bit := '1';
signal  vss       :     bit := '0';
begin

shift: entity work.Shifter
port map(
            shift_lsl => shift_lsl,
            shift_lsr => shift_lsr,
            shift_asr => shift_asr,
            shift_ror => shift_ror,
            shift_rrx => shift_rrx,
            shift_val => shift_val,
            din       => din,
            cin       => cin,
            dout      => dout,
            cout      => cout,
            vdd       => vdd,
            vss       => vss
         );
process
begin
    shift_ror <= '1';
    shift_val <= "00010";
    din       <= std_logic_vector(to_unsigned(32654, 32));
    wait for 5 ns;
    report "dout = " & integer'image(to_integer(unsigned(dout)));
    WAIT;
end process;

end Structurel;