254 lines
6.1 KiB
VHDL
254 lines
6.1 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity EXec is
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port(
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-- Decode interface synchro
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dec2exe_empty : in Std_logic;
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exe_pop : out Std_logic;
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-- Decode interface operands
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dec_op1 : in Std_Logic_Vector(31 downto 0); -- first alu input
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dec_op2 : in Std_Logic_Vector(31 downto 0); -- shifter input
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dec_exe_dest : in Std_Logic_Vector(3 downto 0) ; -- Rd destination
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dec_exe_wb : in Std_Logic; -- Rd destination write back
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dec_flag_wb : in Std_Logic; -- CSPR modifiy
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-- Decode to mem interface
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dec_mem_data : in Std_Logic_Vector(31 downto 0); -- data to MEM W
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dec_mem_dest : in Std_Logic_Vector(3 downto 0) ; -- Destination MEM R
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dec_pre_index : in Std_logic;
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dec_mem_lw : in Std_Logic;
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dec_mem_lb : in Std_Logic;
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dec_mem_sw : in Std_Logic;
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dec_mem_sb : in Std_Logic;
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-- Shifter command
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dec_shift_lsl : in Std_Logic;
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dec_shift_lsr : in Std_Logic;
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dec_shift_asr : in Std_Logic;
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dec_shift_ror : in Std_Logic;
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dec_shift_rrx : in Std_Logic;
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dec_shift_val : in Std_Logic_Vector(4 downto 0);
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dec_cy : in Std_Logic;
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-- Alu operand selection
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dec_comp_op1 : in Std_Logic;
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dec_comp_op2 : in Std_Logic;
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dec_alu_cy : in Std_Logic;
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-- Alu command
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dec_alu_cmd : in Std_Logic_Vector(1 downto 0);
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-- Exe bypass to decod
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exe_res : out Std_Logic_Vector(31 downto 0);
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exe_c : out Std_Logic;
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exe_v : out Std_Logic;
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exe_n : out Std_Logic;
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exe_z : out Std_Logic;
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exe_dest : out Std_Logic_Vector(3 downto 0); -- Rd destination
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exe_wb : out Std_Logic; -- Rd destination write back
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exe_flag_wb : out Std_Logic; -- CSPR modifiy
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-- Mem interface
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exe_mem_adr : out Std_Logic_Vector(31 downto 0); -- Alu res register
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exe_mem_data : out Std_Logic_Vector(31 downto 0);
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exe_mem_dest : out Std_Logic_Vector(3 downto 0);
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exe_mem_lw : out Std_Logic;
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exe_mem_lb : out Std_Logic;
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exe_mem_sw : out Std_Logic;
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exe_mem_sb : out Std_Logic;
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exe2mem_empty : out Std_logic;
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mem_pop : in Std_logic;
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-- global interface
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ck : in Std_logic;
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reset_n : in Std_logic;
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vdd : in bit;
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vss : in bit);
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end EXec;
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----------------------------------------------------------------------
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architecture Behavior OF EXec is
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-- creation des components utilisés par EXEC
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component alu
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port ( op1 : in Std_Logic_Vector(31 downto 0);
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op2 : in Std_Logic_Vector(31 downto 0);
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cin : in Std_Logic;
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cmd : in Std_Logic_Vector(1 downto 0);
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res : out Std_Logic_Vector(31 downto 0);
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cout : out Std_Logic;
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z : out Std_Logic;
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n : out Std_Logic;
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v : out Std_Logic;
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vdd : in bit;
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vss : in bit);
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end component;
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component shifter
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port (
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shift_lsl : in Std_Logic;
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shift_lsr : in Std_Logic;
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shift_asr : in Std_Logic;
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shift_ror : in Std_Logic; -- rotation sans extension
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shift_rrx : in Std_Logic; -- avec extension
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shift_val : in Std_Logic_Vector(4 downto 0);
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din : in Std_Logic_Vector(31 downto 0);
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cin : in Std_Logic;
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dout : out Std_Logic_Vector(31 downto 0);
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cout : out Std_Logic;
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-- global interface
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vdd : in bit;
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vss : in bit
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);
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end component;
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component fifo_72b
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port(
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din : in std_logic_vector(71 downto 0);
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dout : out std_logic_vector(71 downto 0);
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-- commands
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push : in std_logic;
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pop : in std_logic;
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-- flags
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full : out std_logic;
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empty : out std_logic;
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reset_n : in std_logic;
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ck : in std_logic;
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vdd : in bit;
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vss : in bit
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);
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end component;
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-- signal reliant les instances
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-- signal sortant du shifter
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signal shifter_op2 : std_logic_vector(31 downto 0);
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signal shifter_op2_carry : std_logic;
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-- signal entrant de l'alu
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signal alu_op1_in, alu_op2_in : std_logic_vector(31 downto 0);
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-- signal sortant de l'alu
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signal alu_value_out : std_logic_vector(31 downto 0);
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signal alu_value_cout : std_logic;
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-- signal entrant fifo
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signal mem_adr : std_logic_vector(31 downto 0);
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signal exe_push, exe2mem_full : std_logic;
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begin
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-- Component instantiation.
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-- shifter
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shifter_int : shifter
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port map (
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shift_lsl => dec_shift_lsl,
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shift_lsr => dec_shift_lsr,
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shift_asr => dec_shift_asr,
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shift_ror => dec_shift_ror,
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shift_rrx => dec_shift_rrx,
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shift_val => dec_shift_val,
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din => dec_op2,
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cin => dec_cy,
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dout => shifter_op2,
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cout => shifter_op2_carry,
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-- global interface
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vdd => vdd,
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vss => vss
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);
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-- l'alu
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alu_inst : alu
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port map (
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op1 => alu_op1_in,
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op2 => alu_op2_in,
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cin => dec_alu_cy,
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cmd => dec_alu_cmd,
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res => alu_value_out,
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cout => alu_value_cout,
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z => exe_z,
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n => exe_n,
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v => exe_v,
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-- global interface
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vdd => vdd,
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vss => vss
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);
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-- étage de pipeline entre exec et mem
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exec2mem : fifo_72b
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port map ( din(71) => dec_mem_lw,
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din(70) => dec_mem_lb,
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din(69) => dec_mem_sw,
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din(68) => dec_mem_sb,
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din(67 downto 64) => dec_mem_dest,
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din(63 downto 32) => dec_mem_data,
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din(31 downto 0) => mem_adr,
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dout(71) => exe_mem_lw,
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dout(70) => exe_mem_lb,
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dout(69) => exe_mem_sw,
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dout(68) => exe_mem_sb,
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dout(67 downto 64) => exe_mem_dest,
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dout(63 downto 32) => exe_mem_data,
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dout(31 downto 0) => exe_mem_adr,
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push => exe_push,
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pop => mem_pop,
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empty => exe2mem_empty,
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full => exe2mem_full,
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reset_n => reset_n,
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ck => ck,
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vdd => vdd,
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vss => vss
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);
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-- multiplexeurs entrée ALU
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alu_op1_in <= (not dec_op1) when dec_comp_op1='1' else dec_op1;
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alu_op2_in <= (not shifter_op2) when dec_comp_op2='1' else shifter_op2;
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-- bypass 2 decod
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-- resultat ALU
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exe_res <= alu_value_out;
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-- carry flag
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exe_c <= alu_value_cout;
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-- sortie mutex entre ALU et fifo
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mem_adr <= (dec_op1) when dec_pre_index='1' else alu_value_out;
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-- Sortie restante
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-- exe_pop <= dec2exe_empty;
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-- exe_dest <= dec_exe_dest;
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-- exe_wb <= dec_exe_wb;
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-- exe_flag_wb <= dec_flag_wb;
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end Behavior;
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