2021-10-26 19:06:02 +02:00
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library ieee;
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use ieee.math_real.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_1164.all;
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2021-10-27 11:20:58 +02:00
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entity ALU_tb is
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end ALU_tb;
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architecture Structurel of ALU_tb is
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signal op1 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(32654, 32));
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signal op2 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(65877, 32));
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signal cin : std_logic := '0';
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signal cmd : std_logic_vector(1 downto 0) := "00";
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signal res : std_logic_vector(31 downto 0) := (others => '0');
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signal cout : std_logic;
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signal z : std_logic;
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signal n : std_logic;
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signal v : std_logic;
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signal vdd : bit := '1';
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signal vss : bit := '0';
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2021-10-26 19:06:02 +02:00
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begin
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2021-10-27 11:20:58 +02:00
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ALU_ins: entity work.ALU
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port map(
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op1 => op1,
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op2 => op2,
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cin => cin,
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cmd => cmd,
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res => res,
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cout => cout,
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z => z,
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n => n,
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v => v,
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vdd => vdd,
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vss => vss
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);
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process
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begin
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wait for 5 fs;
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cmd <= "00";
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wait for 5 fs;
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report "op1 = " & integer'image(to_integer(unsigned(op1)));
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report "op2 = " & integer'image(to_integer(unsigned(op2)));
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report "res = " & integer'image(to_integer(unsigned(res)));
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assert z/='1'report "z";
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assert n/='1'report "n";
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assert v/='1'report "v";
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wait for 5 fs;
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cmd <= "01";
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wait for 5 fs;
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report "op1 = " & integer'image(to_integer(unsigned(op1)));
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report "op2 = " & integer'image(to_integer(unsigned(op2)));
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report "res = " & integer'image(to_integer(unsigned(res)));
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assert z/='1'report "z";
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assert n/='1'report "n";
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assert v/='1'report "v";
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wait for 5 fs;
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cmd <= "10";
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wait for 5 fs;
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report "op1 = " & integer'image(to_integer(unsigned(op1)));
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report "op2 = " & integer'image(to_integer(unsigned(op2)));
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report "res = " & integer'image(to_integer(unsigned(res)));
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assert z/='1'report "z";
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assert n/='1'report "n";
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assert v/='1'report "v";
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wait for 5 fs;
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cmd <= "11";
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wait for 5 fs;
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report "op1 = " & integer'image(to_integer(unsigned(op1)));
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report "op2 = " & integer'image(to_integer(unsigned(op2)));
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report "res = " & integer'image(to_integer(unsigned(res)));
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assert z/='1'report "z";
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assert n/='1'report "n";
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assert v/='1'report "v";
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wait for 5 fs;
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cmd <= "00";
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wait for 5 fs;
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report "op1 = " & integer'image(to_integer(unsigned(op1)));
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report "op2 = " & integer'image(to_integer(unsigned(op2)));
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report "res = " & integer'image(to_integer(unsigned(res)));
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assert z/='1'report "z";
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assert n/='1'report "n";
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assert v/='1'report "v";
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wait for 5 fs;
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cmd <= "00";
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wait for 5 fs;
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report "op1 = " & integer'image(to_integer(unsigned(op1)));
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report "op2 = " & integer'image(to_integer(unsigned(op2)));
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report "res = " & integer'image(to_integer(unsigned(res)));
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assert z/='1'report "z";
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assert n/='1'report "n";
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assert v/='1'report "v";
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wait for 50 fs;
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wait;
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end process;
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end Structurel;
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