55 lines
994 B
VHDL
55 lines
994 B
VHDL
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library ieee;
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use ieee.math_real.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_1164.all;
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-----------------------------------------------------------------
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-- adder 32 bit
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-----------------------------------------------------------------
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entity adder32_ent is
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port (
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cin : IN std_logic;
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i0, i1 : IN std_logic_vector(31 downto 0);
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q : OUT std_logic_vector(31 downto 0);
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cout : OUT std_logic
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);
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end entity;
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architecture adder32 of adder32_ent is
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signal co : std_logic_vector(31 downto 0);
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begin
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adder32_0 : entity work.adder1_ent
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port map (
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i0 => i0(0),
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i1 => i1(0),
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cin => cin,
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q => q(0),
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cout => co(0)
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);
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loop_29: for i in 1 to 30 generate
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adder32_n : entity work.adder1_ent
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port map (
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i0 => i0(i),
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i1 => i1(i),
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cin => co(i-1),
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q => q(i),
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cout => co(i)
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);
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end generate loop_29;
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adder32_31 : entity work.adder1_ent
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port map (
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i0 => i0(31),
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i1 => i1(31),
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cin => co(30),
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q => q(31),
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cout => cout
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);
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end adder32;
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