69 lines
1.6 KiB
VHDL
69 lines
1.6 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.math_real.all;
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use ieee.numeric_std.all;
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entity registre_dcc_tb is
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end registre_dcc_tb;
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architecture tb of registre_dcc_tb is
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signal trame_dcc : std_logic_vector(50 downto 0);
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signal clk : std_logic := '0';
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signal reset, shift, load : std_logic;
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signal sout : std_logic;
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signal trame_dcc_tb : std_logic_vector(50 downto 0);
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begin
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clk <= not clk after 2 ns;
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dcc: entity work.registre_dcc
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port map(
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trame_dcc => trame_dcc,
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clk => clk,
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reset => reset,
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shift => shift,
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load => load,
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sout => sout
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);
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process
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begin
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trame_dcc_tb <= "111011111111110110010010001110110010010111011101001";
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reset <= '1';
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wait for 10 ns;
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reset <= '0';
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assert (sout = '0') report "invalid sout value at reset (we have "
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& integer'image(to_integer(unsigned'("" & sout)))
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& ")"
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severity error;
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load <= '1';
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trame_dcc <= trame_dcc_tb;
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wait for 10 ns;
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load <= '0';
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assert (sout = '1') report "invalid sout value at load (we have "
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& integer'image(to_integer(unsigned'("" & sout)))
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& ")"
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severity error;
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for i in 0 to 60 loop
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assert (sout = trame_dcc_tb(50)) report "sout != sout_tb pour le bit "
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& integer'image(i)
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& "on a : "
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& integer'image(to_integer(unsigned'("" & sout)))
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& ")"
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severity error;
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trame_dcc_tb <= trame_dcc_tb(49 downto 0) & '0';
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shift <= '1';
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wait for 15 ns;
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shift <= '0';
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wait for 15 ns;
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end loop;
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assert(false) report "Test Register_DCC terminé" severity warning;
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wait;
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end process;
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end tb;
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