library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;

entity registre_dcc_tb is
end registre_dcc_tb;

architecture tb of registre_dcc_tb is
	signal trame_dcc : std_logic_vector(50 downto 0);
	signal clk : std_logic := '0'; 
	signal reset, shift, load : std_logic;
	signal sout : std_logic;
	signal trame_dcc_tb : std_logic_vector(50 downto 0);
begin
	clk <= not clk after 2 ns;
	
	dcc: entity work.registre_dcc 
	port map(
		trame_dcc => trame_dcc,
		clk => clk,
		reset => reset,
		shift => shift,
		load => load,
		sout => sout
	);
	
	process
	begin
		trame_dcc_tb <= "111011111111110110010010001110110010010111011101001";
		
		reset <= '1';
		wait for 10 ns;
		reset <= '0';
		assert (sout = '0') report "invalid sout value at reset (we have " 
			& integer'image(to_integer(unsigned'("" & sout))) 
			& ")" 
			severity error;

		load <= '1';
		trame_dcc <= trame_dcc_tb;
		wait for 10 ns;
		load <= '0';
		assert (sout = '1') report "invalid sout value at load (we have " 
			& integer'image(to_integer(unsigned'("" & sout))) 
			& ")" 
			severity error;

		for i in 0 to 60 loop
			assert (sout = trame_dcc_tb(50)) report "sout != sout_tb pour le bit " 
				& integer'image(i)
				& "on a : "
				& integer'image(to_integer(unsigned'("" & sout)))
				& ")"
				severity error;
			trame_dcc_tb <= trame_dcc_tb(49 downto 0) & '0';
			shift <= '1';
			wait for 15 ns;
			shift <= '0';
			wait for 15 ns;
		end loop;
		
		assert(false) report "Test Register_DCC terminé" severity warning;
		wait;

	end process;

end tb;