Registre_DCC fonctionnel
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----------------------------------------------------------------------------------
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-- Company: SORBONNE UNIVERSITE
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-- Designed by: J.DENOULET, Winter 2021
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--
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-- Module Name: COMPTEUR_TEMPO - Behavioral
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-- Project Name: Centrale DCC
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-- Target Devices: NEXYS 4 DDR
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--
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-- Compteur de Temporisation de la Centrale DCC
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--
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-- Après détection du passage à 1 de la commande Start_Tempo,
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-- le module compte 6 ms et positionne à 1 la sortie Fin_Tempo
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--
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-- Pour être détectée, la commande Start_Tempo doit être mise à 1
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-- pendant au moins 1 période de l'horloge 100 MHz
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--
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-- Quand Fin_Tempo pase à 1, la sortie reste dans cet état tant que
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-- Start_Tempo est à 1.
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-- Dès la détection du retour à 0 de Start_Tempo,
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-- Fin_Tempo repasse à 0.
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--
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-- De cette manière, la durée de minimale l'impulsion à 1 de
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-- Fin_Tempo sera d'un cycle de l'horloge 100 MHz.
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-- Cela est a priori suffisant pour sa bonne détection
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-- par la MAE de la Centrale DCC.
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity COMPTEUR_TEMPO is
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Port ( Clk : in STD_LOGIC; -- Horloge 100 MHz
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Reset : in STD_LOGIC; -- Reset Asynchrone
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Clk1M : in STD_LOGIC; -- Horloge 1 MHz
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Start_Tempo : in STD_LOGIC; -- Commande de Démarrage de la Temporisation
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Fin_Tempo : out STD_LOGIC -- Drapeau de Fin de la Temporisation
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);
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end COMPTEUR_TEMPO;
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architecture Behavioral of COMPTEUR_TEMPO is
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signal Q: std_logic_vector(1 downto 0); -- Etat Séquenceur
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signal Raz_CPt,Inc_Cpt: std_logic; -- Commandes Compteur
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signal Fin_Cpt: std_logic; -- Drapeau de Fin de Comptage
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-- Compteur de Temporisation
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signal Cpt : INTEGER range 0 to 10000; -- Compteur (6000 = 6 ms)
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signal En_Tempo : STD_LOGIC; -- Commande d'Incrémentation
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begin
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-- Séquenceur
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process(Clk,Reset)
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begin
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if Reset='1' then Q <= "00";
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elsif rising_edge(Clk) then
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Q(1) <= ((not Q(1)) and Q(0) and Fin_Cpt) or (Q(1) and Start_Tempo);
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Q(0) <= Start_Tempo or ((not Q(1)) and Q(0));
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end if;
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end process;
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-- Sorties Séquenceur
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Raz_Cpt <= Q(1) xnor Q(0);
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Inc_Cpt <= (not Q(1)) and Q(0);
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Fin_Tempo <= Q(1) and Q(0);
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-- Compteur de Temporisation
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process (Clk1M, Reset)
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begin
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-- Reset Asynchrone
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if (Reset) = '1' then
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Cpt <= 0;
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elsif rising_edge (Clk1M) then
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if Raz_Cpt = '1' then Cpt <= 0;
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elsif Inc_Cpt = '1' then Cpt <= Cpt + 1;
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end if;
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end if;
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end process;
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Fin_Cpt <= '1' when (Cpt = 5999) else '0';
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end Behavioral;
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----------------------------------------------------------------------------------
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-- Company: UPMC
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-- Designed by: E.PIMOR S.HAMOUM, Spring 2017
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-- Revision by: J.DENOULET, Summer 2017
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--
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-- Module Name: CLK_DIV - Behavioral
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-- Project Name: Centrale DCC
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-- Target Devices: NEXYS 4 DDR
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--
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-- Diviseur d'Horloge: 100 MHé --> 1 MHz
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity CLK_DIV is
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Port ( Reset : in STD_LOGIC; -- Reset Asynchrone
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Clk_In : in STD_LOGIC; -- Horloge 100 MHz de la carte Nexys
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Clk_Out : out STD_LOGIC); -- Horloge 1 MHz de sortie
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end CLK_DIV;
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architecture Behavioral of CLK_DIV is
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signal Div : INTEGER range 0 to 49; -- Compteur de cycles d'horloge
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signal Clk_Temp : STD_LOGIC; -- Signal temporaire
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begin
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Clk_Out <= Clk_Temp; -- Affectation du Port de Sortie
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process (Clk_In, Reset)
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begin
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-- Reset Asynchrone
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if Reset = '1' then
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Clk_Temp <= '0';
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-- A Chaque Front d'Horloge
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elsif rising_edge (Clk_In) then
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Div <= Div + 1; -- Incrémentation du Compteur
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if Div = 49 then -- Inversion du Signal d'Horloge Tous les 50 Cycles
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Div <= 0;
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Clk_Temp <= not Clk_Temp;
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end if;
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end if;
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end process;
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end Behavioral;
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@ -0,0 +1,159 @@
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----------------------------------------------------------------------------------
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-- Company: SORBONNE UNIVERSITE
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-- Designed by: J.DENOULET, Winter 2021
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--
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-- Module Name: DCC_FRAME_GENERATOR - Behavioral
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-- Project Name: Centrale DCC
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-- Target Devices: NEXYS 4 DDR
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--
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-- Générateur de Trames de Test pour la Centrale DCC
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity DCC_FRAME_GENERATOR is
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Port ( Interrupteur : in STD_LOGIC_VECTOR(7 downto 0); -- Interrupteurs de la Carte
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Trame_DCC : out STD_LOGIC_VECTOR(50 downto 0)); -- Trame DCC de Test
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end DCC_FRAME_GENERATOR;
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architecture Behavioral of DCC_FRAME_GENERATOR is
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begin
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-- Génération d'une Trame selon l'Interrupteur Tiré vers le Haut
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-- Si Plusieurs Interupteurs Sont Tirés, Celui de Gauche Est Prioritaire
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-- Compléter les Trames pour Réaliser les Tests Voulus
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process(Interrupteur)
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begin
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-- Interrupteur 7 Activé
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--> Trame Marche Avant du Train d'Adresse i
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if Interrupteur(7)='1' then
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Trame_DCC <= "1111111111111111111111" -- Préambule
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& "0" -- Start Bit
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& "00000010" -- Champ Adresse (adresse 2 sans raison particuliere )
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& "0" -- Start Bit
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& "01100011" -- Champ Commande (vitesse step 3 sans raison particuliere)
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& "0" -- Start Bit
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& "01100001" -- Champ Contrôle
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& "1" ; -- Stop Bit
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-- Interrupteur 6 Activé
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--> Trame Marche Arrière du Train d'Adresse i
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elsif Interrupteur(6)='1' then
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Trame_DCC <= "1111111111111111111111" -- Préambule
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& "0" -- Start Bit
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& "00000010" -- Champ Adresse
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& "0" -- Start Bit
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& "01000011" -- Champ Commande
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& "0" -- Start Bit
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& "01000001" -- Champ Contrôle
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& "1" ; -- Stop Bit
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-- Interrupteur 5 Activé
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--> Allumage des Phares du Train d'Adresse i
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elsif Interrupteur(5)='1' then
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Trame_DCC <= "1111111111111111111111" -- Préambule
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& "0" -- Start Bit
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& "00000010" -- Champ Adresse
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& "0" -- Start Bit
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& "10010000" -- Champ Commande
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& "0" -- Start Bit
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& "10010010" -- Champ Contrôle
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& "1" ; -- Stop Bit
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-- Interrupteur 4 Activé
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--> Extinction des Phares du Train d'Adresse i
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elsif Interrupteur(4)='1' then
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Trame_DCC <= "1111111111111111111111" -- Préambule
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& "0" -- Start Bit
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& "00000010" -- Champ Adresse
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& "0" -- Start Bit
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& "10000000" -- Champ Commande
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& "0" -- Start Bit
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& "10000010" -- Champ Contrôle
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& "1" ; -- Stop Bit
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-- Interrupteur 3 Activé
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--> Activation du Klaxon (Fonction F11) du Train d'Adresse i
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elsif Interrupteur(3)='1' then
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Trame_DCC <= "1111111111111111111111" -- Préambule
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& "0" -- Start Bit
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& "00000010" -- Champ Adresse
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& "0" -- Start Bit
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& "10100100" -- Champ Commande
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& "0" -- Start Bit
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& "10100110" -- Champ Contrôle
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& "1" ; -- Stop Bit
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-- Interrupteur 2 Activé
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--> Réamorçage du Klaxon (Fonction F11) du Train d'Adresse i
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elsif Interrupteur(2)='1' then
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Trame_DCC <= "1111111111111111111111" -- Préambule
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& "0" -- Start Bit
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& "00000010" -- Champ Adresse
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& "0" -- Start Bit
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& "10100000" -- Champ Commande
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& "0" -- Start Bit
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& "10100010" -- Champ Contrôle
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& "1" ; -- Stop Bit
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-- Interrupteur 1 Activé
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--> Annonce SNCF (Fonction F13) du Train d'Adresse i
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elsif Interrupteur(1)='1' then
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Trame_DCC <= "11111111111111" -- Préambule
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& "0" -- Start Bit
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& "00000010" -- Champ Adresse
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& "0" -- Start Bit
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& "11011110" -- Champ Commande (Octet 1)
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& "0" -- Start Bit
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& "00000001" -- Champ Commande (Octet 2)
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& "0" -- Start Bit
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& "11011111" -- Champ Contrôle
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& "1" ; -- Stop Bit
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-- Interrupteur 0 Activé
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--> Annonce SNCF (Fonction F13) du Train d'Adresse i
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elsif Interrupteur(0)='1' then
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Trame_DCC <= "11111111111111" -- Préambule
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& "0" -- Start Bit
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& "00000010" -- Champ Adresse
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& "0" -- Start Bit
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& "11011110" -- Champ Commande (Octet 1)
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& "0" -- Start Bit
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& "00000000" -- Champ Commande (Octet 2)
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& "0" -- Start Bit
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& "11011110" -- Champ Contrôle
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& "1" ; -- Stop Bit
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-- Aucun Interrupteur Activé
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--> Arrêt du Train d'Adresse i
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else
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Trame_DCC <= "1111111111111111111111" -- Préambule
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& "0" -- Start Bit
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& "00000010" -- Champ Adresse
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& "0" -- Start Bit
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& "01100000" -- Champ Commande
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& "0" -- Start Bit
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& "01100010" -- Champ Contrôle
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& "1" ; -- Stop Bit
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end process;
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end Behavioral;
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@ -0,0 +1,265 @@
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## This file is a general .xdc for the Nexys4 DDR Rev. C
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## To use it in a project:
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## - uncomment the lines corresponding to used pins
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## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
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## Clock signal
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#set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
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#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}];
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##Switches
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#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
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#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
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#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
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#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
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#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
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#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { SW[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
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#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { SW[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
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#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { SW[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
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#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { SW[8] }]; #IO_L24N_T3_34 Sch=sw[8]
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#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { SW[9] }]; #IO_25_34 Sch=sw[9]
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#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { SW[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
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#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { SW[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11]
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#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { SW[12] }]; #IO_L24P_T3_35 Sch=sw[12]
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#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { SW[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
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#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { SW[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
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#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { SW[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
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## LEDs
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#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
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#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
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#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
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#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
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#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { LED[4] }]; #IO_L7P_T1_D09_14 Sch=led[4]
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#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { LED[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5]
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||||||
|
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { LED[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6]
|
||||||
|
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { LED[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7]
|
||||||
|
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { LED[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8]
|
||||||
|
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { LED[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9]
|
||||||
|
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { LED[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10]
|
||||||
|
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { LED[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11]
|
||||||
|
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { LED[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12]
|
||||||
|
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { LED[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13]
|
||||||
|
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { LED[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14]
|
||||||
|
#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { LED[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15]
|
||||||
|
|
||||||
|
#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { LED16_B }]; #IO_L5P_T0_D06_14 Sch=led16_b
|
||||||
|
#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { LED16_G }]; #IO_L10P_T1_D14_14 Sch=led16_g
|
||||||
|
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { LED16_R }]; #IO_L11P_T1_SRCC_14 Sch=led16_r
|
||||||
|
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { LED17_B }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b
|
||||||
|
#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { LED17_G }]; #IO_0_14 Sch=led17_g
|
||||||
|
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { LED17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r
|
||||||
|
|
||||||
|
|
||||||
|
##7 segment display
|
||||||
|
|
||||||
|
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { CA }]; #IO_L24N_T3_A00_D16_14 Sch=ca
|
||||||
|
#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { CB }]; #IO_25_14 Sch=cb
|
||||||
|
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { CC }]; #IO_25_15 Sch=cc
|
||||||
|
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { CD }]; #IO_L17P_T2_A26_15 Sch=cd
|
||||||
|
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { CE }]; #IO_L13P_T2_MRCC_14 Sch=ce
|
||||||
|
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { CF }]; #IO_L19P_T3_A10_D26_14 Sch=cf
|
||||||
|
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { CG }]; #IO_L4P_T0_D04_14 Sch=cg
|
||||||
|
|
||||||
|
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
|
||||||
|
|
||||||
|
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
|
||||||
|
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
|
||||||
|
#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
|
||||||
|
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
|
||||||
|
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
|
||||||
|
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
|
||||||
|
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { AN[6] }]; #IO_L23P_T3_35 Sch=an[6]
|
||||||
|
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
|
||||||
|
|
||||||
|
|
||||||
|
##Buttons
|
||||||
|
|
||||||
|
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { CPU_RESETN }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
|
||||||
|
|
||||||
|
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { BTNC }]; #IO_L9P_T1_DQS_14 Sch=btnc
|
||||||
|
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { BTNU }]; #IO_L4N_T0_D05_14 Sch=btnu
|
||||||
|
#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { BTNL }]; #IO_L12P_T1_MRCC_14 Sch=btnl
|
||||||
|
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr
|
||||||
|
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { BTND }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
|
||||||
|
|
||||||
|
|
||||||
|
##Pmod Headers
|
||||||
|
|
||||||
|
|
||||||
|
##Pmod Header JA
|
||||||
|
|
||||||
|
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { JA[1] }]; #IO_L20N_T3_A19_15 Sch=ja[1]
|
||||||
|
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { JA[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2]
|
||||||
|
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { JA[3] }]; #IO_L21P_T3_DQS_15 Sch=ja[3]
|
||||||
|
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { JA[4] }]; #IO_L18N_T2_A23_15 Sch=ja[4]
|
||||||
|
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { JA[7] }]; #IO_L16N_T2_A27_15 Sch=ja[7]
|
||||||
|
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { JA[8] }]; #IO_L16P_T2_A28_15 Sch=ja[8]
|
||||||
|
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { JA[9] }]; #IO_L22N_T3_A16_15 Sch=ja[9]
|
||||||
|
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { JA[10] }]; #IO_L22P_T3_A17_15 Sch=ja[10]
|
||||||
|
|
||||||
|
|
||||||
|
##Pmod Header JB
|
||||||
|
|
||||||
|
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { JB[1] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1]
|
||||||
|
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { JB[2] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2]
|
||||||
|
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { JB[3] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3]
|
||||||
|
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { JB[4] }]; #IO_L15P_T2_DQS_15 Sch=jb[4]
|
||||||
|
#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { JB[7] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7]
|
||||||
|
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { JB[8] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8]
|
||||||
|
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { JB[9] }]; #IO_0_15 Sch=jb[9]
|
||||||
|
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { JB[10] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10]
|
||||||
|
|
||||||
|
|
||||||
|
##Pmod Header JC
|
||||||
|
|
||||||
|
#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { JC[1] }]; #IO_L23N_T3_35 Sch=jc[1]
|
||||||
|
#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { JC[2] }]; #IO_L19N_T3_VREF_35 Sch=jc[2]
|
||||||
|
#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { JC[3] }]; #IO_L22N_T3_35 Sch=jc[3]
|
||||||
|
#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { JC[4] }]; #IO_L19P_T3_35 Sch=jc[4]
|
||||||
|
#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { JC[7] }]; #IO_L6P_T0_35 Sch=jc[7]
|
||||||
|
#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { JC[8] }]; #IO_L22P_T3_35 Sch=jc[8]
|
||||||
|
#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { JC[9] }]; #IO_L21P_T3_DQS_35 Sch=jc[9]
|
||||||
|
#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { JC[10] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10]
|
||||||
|
|
||||||
|
|
||||||
|
##Pmod Header JD
|
||||||
|
|
||||||
|
#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { JD[1] }]; #IO_L21N_T3_DQS_35 Sch=jd[1]
|
||||||
|
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { JD[2] }]; #IO_L17P_T2_35 Sch=jd[2]
|
||||||
|
#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { JD[3] }]; #IO_L17N_T2_35 Sch=jd[3]
|
||||||
|
#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { JD[4] }]; #IO_L20N_T3_35 Sch=jd[4]
|
||||||
|
#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { JD[7] }]; #IO_L15P_T2_DQS_35 Sch=jd[7]
|
||||||
|
#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { JD[8] }]; #IO_L20P_T3_35 Sch=jd[8]
|
||||||
|
#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { JD[9] }]; #IO_L15N_T2_DQS_35 Sch=jd[9]
|
||||||
|
#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { JD[10] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10]
|
||||||
|
|
||||||
|
|
||||||
|
##Pmod Header JXADC
|
||||||
|
|
||||||
|
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { XA_N[1] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1]
|
||||||
|
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { XA_P[1] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1]
|
||||||
|
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { XA_N[2] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2]
|
||||||
|
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { XA_P[2] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2]
|
||||||
|
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { XA_N[3] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3]
|
||||||
|
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { XA_P[3] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3]
|
||||||
|
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { XA_N[4] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4]
|
||||||
|
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { XA_P[4] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4]
|
||||||
|
|
||||||
|
|
||||||
|
##VGA Connector
|
||||||
|
|
||||||
|
#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0]
|
||||||
|
#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1]
|
||||||
|
#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2]
|
||||||
|
#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3]
|
||||||
|
|
||||||
|
#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0]
|
||||||
|
#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1]
|
||||||
|
#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2]
|
||||||
|
#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3]
|
||||||
|
|
||||||
|
#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0]
|
||||||
|
#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[1] }]; #IO_L4N_T0_35 Sch=vga_b[1]
|
||||||
|
#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2]
|
||||||
|
#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[3] }]; #IO_L4P_T0_35 Sch=vga_b[3]
|
||||||
|
|
||||||
|
#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { VGA_HS }]; #IO_L4P_T0_15 Sch=vga_hs
|
||||||
|
#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { VGA_VS }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs
|
||||||
|
|
||||||
|
|
||||||
|
##Micro SD Connector
|
||||||
|
|
||||||
|
#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { SD_RESET }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset
|
||||||
|
#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { SD_CD }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd
|
||||||
|
#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { SD_SCK }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck
|
||||||
|
#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { SD_CMD }]; #IO_L16N_T2_35 Sch=sd_cmd
|
||||||
|
#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0]
|
||||||
|
#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1]
|
||||||
|
#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2]
|
||||||
|
#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3]
|
||||||
|
|
||||||
|
|
||||||
|
##Accelerometer
|
||||||
|
|
||||||
|
#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { ACL_MISO }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso
|
||||||
|
#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { ACL_MOSI }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi
|
||||||
|
#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { ACL_SCLK }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk
|
||||||
|
#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { ACL_CSN }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn
|
||||||
|
#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1]
|
||||||
|
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2]
|
||||||
|
|
||||||
|
|
||||||
|
##Temperature Sensor
|
||||||
|
|
||||||
|
#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { TMP_SCL }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl
|
||||||
|
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { TMP_SDA }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda
|
||||||
|
#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { TMP_INT }]; #IO_L6N_T0_VREF_15 Sch=tmp_int
|
||||||
|
#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { TMP_CT }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct
|
||||||
|
|
||||||
|
##Omnidirectional Microphone
|
||||||
|
|
||||||
|
#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { M_CLK }]; #IO_25_35 Sch=m_clk
|
||||||
|
#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { M_DATA }]; #IO_L24N_T3_35 Sch=m_data
|
||||||
|
#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { M_LRSEL }]; #IO_0_35 Sch=m_lrsel
|
||||||
|
|
||||||
|
|
||||||
|
##PWM Audio Amplifier
|
||||||
|
|
||||||
|
#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { AUD_PWM }]; #IO_L4N_T0_15 Sch=aud_pwm
|
||||||
|
#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { AUD_SD }]; #IO_L6P_T0_15 Sch=aud_sd
|
||||||
|
|
||||||
|
|
||||||
|
##USB-RS232 Interface
|
||||||
|
|
||||||
|
#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { UART_TXD_IN }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in
|
||||||
|
#set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { UART_RXD_OUT }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out
|
||||||
|
#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { UART_CTS }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts
|
||||||
|
#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { UART_RTS }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts
|
||||||
|
|
||||||
|
##USB HID (PS/2)
|
||||||
|
|
||||||
|
#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { PS2_CLK }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk
|
||||||
|
#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { PS2_DATA }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data
|
||||||
|
|
||||||
|
|
||||||
|
##SMSC Ethernet PHY
|
||||||
|
|
||||||
|
#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDC }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc
|
||||||
|
#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDIO }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio
|
||||||
|
#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { ETH_RSTN }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn
|
||||||
|
#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { ETH_CRSDV }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv
|
||||||
|
#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXERR }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr
|
||||||
|
#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0]
|
||||||
|
#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1]
|
||||||
|
#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXEN }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen
|
||||||
|
#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0]
|
||||||
|
#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1]
|
||||||
|
#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { ETH_REFCLK }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk
|
||||||
|
#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { ETH_INTN }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn
|
||||||
|
|
||||||
|
|
||||||
|
##Quad SPI Flash
|
||||||
|
|
||||||
|
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
|
||||||
|
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
|
||||||
|
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
|
||||||
|
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
|
||||||
|
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,45 @@
|
||||||
|
library ieee;
|
||||||
|
use ieee.std_logic_1164.all;
|
||||||
|
|
||||||
|
entity registre_dcc is
|
||||||
|
port(
|
||||||
|
trame_dcc : in std_logic_vector(50 downto 0);
|
||||||
|
clk : in std_logic;
|
||||||
|
reset : in std_logic;
|
||||||
|
shift : in std_logic;
|
||||||
|
load : in std_logic;
|
||||||
|
sout : out std_logic
|
||||||
|
|
||||||
|
);
|
||||||
|
|
||||||
|
end registre_dcc;
|
||||||
|
|
||||||
|
architecture behaviour of registre_dcc is
|
||||||
|
signal sr : std_logic_vector(50 downto 0);
|
||||||
|
signal lc_shift : std_logic := '0';
|
||||||
|
|
||||||
|
begin
|
||||||
|
process(clk, reset, shift)
|
||||||
|
begin
|
||||||
|
if reset = '1' then
|
||||||
|
sr <= ( others => '0' );
|
||||||
|
|
||||||
|
elsif rising_edge(clk) then
|
||||||
|
if load = '1' then
|
||||||
|
sr <= trame_dcc;
|
||||||
|
|
||||||
|
elsif shift = '1' and lc_shift = '0' then
|
||||||
|
sr <= sr(49 downto 0) & '0';
|
||||||
|
lc_shift <= '1';
|
||||||
|
|
||||||
|
elsif shift = '0' then
|
||||||
|
lc_shift <= '0';
|
||||||
|
|
||||||
|
end if;
|
||||||
|
|
||||||
|
end if;
|
||||||
|
|
||||||
|
end process;
|
||||||
|
sout <= sr(50); --sr pas initialisé par défaut
|
||||||
|
|
||||||
|
end behaviour;
|
||||||
|
|
@ -0,0 +1,68 @@
|
||||||
|
library ieee;
|
||||||
|
use ieee.std_logic_1164.all;
|
||||||
|
use ieee.math_real.all;
|
||||||
|
use ieee.numeric_std.all;
|
||||||
|
|
||||||
|
entity registre_dcc_tb is
|
||||||
|
end registre_dcc_tb;
|
||||||
|
|
||||||
|
architecture tb of registre_dcc_tb is
|
||||||
|
signal trame_dcc : std_logic_vector(50 downto 0);
|
||||||
|
signal clk : std_logic := '0';
|
||||||
|
signal reset, shift, load : std_logic;
|
||||||
|
signal sout : std_logic;
|
||||||
|
signal trame_dcc_tb : std_logic_vector(50 downto 0);
|
||||||
|
begin
|
||||||
|
clk <= not clk after 2 ns;
|
||||||
|
|
||||||
|
dcc: entity work.registre_dcc
|
||||||
|
port map(
|
||||||
|
trame_dcc => trame_dcc,
|
||||||
|
clk => clk,
|
||||||
|
reset => reset,
|
||||||
|
shift => shift,
|
||||||
|
load => load,
|
||||||
|
sout => sout
|
||||||
|
);
|
||||||
|
|
||||||
|
process
|
||||||
|
begin
|
||||||
|
trame_dcc_tb <= "111011111111110110010010001110110010010111011101001";
|
||||||
|
|
||||||
|
reset <= '1';
|
||||||
|
wait for 10 ns;
|
||||||
|
reset <= '0';
|
||||||
|
assert (sout = '0') report "invalid sout value at reset (we have "
|
||||||
|
& integer'image(to_integer(unsigned'("" & sout)))
|
||||||
|
& ")"
|
||||||
|
severity error;
|
||||||
|
|
||||||
|
load <= '1';
|
||||||
|
trame_dcc <= trame_dcc_tb;
|
||||||
|
wait for 10 ns;
|
||||||
|
load <= '0';
|
||||||
|
assert (sout = '1') report "invalid sout value at load (we have "
|
||||||
|
& integer'image(to_integer(unsigned'("" & sout)))
|
||||||
|
& ")"
|
||||||
|
severity error;
|
||||||
|
|
||||||
|
for i in 0 to 60 loop
|
||||||
|
assert (sout = trame_dcc_tb(50)) report "sout != sout_tb pour le bit "
|
||||||
|
& integer'image(i)
|
||||||
|
& "on a : "
|
||||||
|
& integer'image(to_integer(unsigned'("" & sout)))
|
||||||
|
& ")"
|
||||||
|
severity error;
|
||||||
|
trame_dcc_tb <= trame_dcc_tb(49 downto 0) & '0';
|
||||||
|
shift <= '1';
|
||||||
|
wait for 15 ns;
|
||||||
|
shift <= '0';
|
||||||
|
wait for 15 ns;
|
||||||
|
end loop;
|
||||||
|
|
||||||
|
assert(false) report "Test Register_DCC terminé" severity warning;
|
||||||
|
wait;
|
||||||
|
|
||||||
|
end process;
|
||||||
|
|
||||||
|
end tb;
|
||||||
Loading…
Reference in New Issue