projet-fpga/DCC_Bit_1_TB.vhd

library ieee;
use ieee.std_logic_1164.all;

entity dcc_bit_1_tb is
end dcc_bit_1_tb;


architecture tb of dcc_bit_1_tb is

	constant ClockPeriod1 : time := 1 us;
	constant ClockPeriod100 : time := 10 ns;

	signal reset : std_logic := '1';
	signal go : std_logic :=  '0'; --inputs
	signal clk_100MHz : std_logic := '0';
	signal clk_1MHz : std_logic := '0'; --clocks
	signal fin, dcc_1 : std_logic; --outputs

begin
	uut : entity work.DCC_Bit_1 port map(
						reset => reset,
						clk_100MHz => clk_100Mhz,
						clk_1MHz => clk_1MHz,
						go => go,
						fin => fin,
						dcc_1 => dcc_1
					);

	clk_100MHz <= not clk_100MHz after ClockPeriod100 / 2;
	clk_1MHz <= not clk_1MHz after ClockPeriod1 / 2;
	
	process
	begin
		reset <= '0';
		wait for 20 ns;
		
		for i in 0 to 50 loop
			go <= '1';
			wait until rising_edge(clk_100MHz);
			go <= '0';

			assert(dcc_1 = '0') report "dcc_1 invalide avant 58us, est à 1 (test" 
				& integer'image(i) & ")";
			wait until rising_edge(dcc_1) for 58 us;
			assert(dcc_1 = '1') report "dcc_1 invalide après 58us, est à 0 (test"
				& integer'image(i) & ")";
			wait until falling_edge(dcc_1) for 58 us;
			assert(dcc_1 = '0') report "dcc_1 invalide après 58us * 2, est à 1 (test"
				& integer'image(i) & ")";

			--assert(false) report "test" & integer'image(i) severity warning;
			assert(fin = '1') report "fin invalide, est à 0";
			
			wait until rising_edge(clk_1MHz);

		end loop;
		
		assert(false) report "Test DCC_Bit_1 terminé" severity warning;
		
		wait;
	end process;
	
end tb;