projet-fpga/DCC_Bit_0.vhd

library ieee;
use ieee.std_logic_1164.all;

entity dcc_bit_0 is 
	port(
		reset : in std_logic;
		clk_100MHz : in std_logic;
		clk_1MHz : in std_logic;
		go : in std_logic;
		fin : out std_logic;
		dcc_0 : out std_logic
	);
end dcc_bit_0;


architecture behaviour of dcc_bit_0 is
	type state is (idle, out_0, out_1);
	signal cs, fs : state;
	signal inc_cpt : std_logic;
	signal cpt : integer range 0 to 200;
	signal out_value : std_logic := '0';
begin
	dcc_0 <= out_value;

	--MAE
	process(clk_100MHz, reset)
	begin
		if reset = '1' then 
			fs <= idle;

		elsif rising_edge(clk_100MHz) then

			if cs = idle then

				fin <= '0';
				out_value <= '0';

				if go = '1' then
					inc_cpt <= '1';
					fs <= out_0;
				end if;

			elsif cs = out_0 then

				out_value <= '0';

				if cpt >= 99 then 
					fs <= out_1;
				end if;

			elsif cs = out_1 then 

				out_value <= '1';

				if cpt >= 199 then
					fs <= idle;
					out_value <= '0';
					fin <= '1';
					inc_cpt <= '0';
				end if;			

			end if;
			cs <= fs;
		end if;

	end process;

	--Compteur de Temporisation
	process(clk_1MHz, reset)
	begin
		if reset = '1' then

			cpt <= 0;

		elsif rising_edge(clk_1MHz) then
        
			if inc_cpt = '1' then
				cpt <= cpt + 1;
			else
				cpt <= 0;
			end if;
        
		end if;
	end process;

	
end behaviour;