241 lines
7.1 KiB
VHDL
241 lines
7.1 KiB
VHDL
library ieee;
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use ieee.math_real.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_1164.all;
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entity shifter_tb is
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end shifter_tb;
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ARCHITECTURE Structurel OF Shifter_tb is
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signal shift_lsl : Std_Logic := '0';
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signal shift_lsr : Std_Logic := '0';
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signal shift_asr : Std_Logic := '0';
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signal shift_ror : Std_Logic := '0';
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signal shift_rrx : Std_Logic := '0';
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signal shift_val : Std_Logic_Vector(4 downto 0);
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signal din : Std_Logic_Vector(31 downto 0);
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signal cin : Std_Logic := '0';
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signal dout : Std_Logic_Vector(31 downto 0);
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signal cout : Std_Logic;
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signal vdd : bit := '1';
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signal vss : bit := '0';
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begin
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shift: entity work.Shifter
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port map(
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shift_lsl => shift_lsl,
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shift_lsr => shift_lsr,
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shift_asr => shift_asr,
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shift_ror => shift_ror,
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shift_rrx => shift_rrx,
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shift_val => shift_val,
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din => din,
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cin => cin,
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dout => dout,
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cout => cout,
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vdd => vdd,
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vss => vss
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);
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process
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-- Variables for the random number
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variable seed1 : positive;
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variable seed2 : positive;
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variable x : real;
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variable y : integer;
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variable vdout : std_logic_vector(31 downto 0);
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variable vcout : std_logic;
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begin
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-- set vdd to 5v
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vdd <= '1';
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-- set vss to gnd
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vss <= '0';
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-- seeds for random number
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seed1 := 1;
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seed2 := 1;
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wait for 1 ns;
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-- lsl
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report "lsl with 32 random values";
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shift_lsl <= '1';
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la : for va in 0 to 31 loop
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uniform(seed1, seed2, x);
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y := integer(floor(x * 31.0)) + 1;
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shift_val <= std_logic_vector(to_unsigned(y, shift_val'length));
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uniform(seed1, seed2, x);
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y := integer(floor(x * 536870911.0));
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din <= std_logic_vector(to_unsigned(y, din'length));
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if (y mod 2) = 0 then
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cin <= '1';
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else
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cin <= '0';
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end if;
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wait for 1 ns;
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vdout := din sll shift_val;
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vcout := 0;
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report "din = " & integer'image(to_integer(unsigned(din)));
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report "shift_val = " & integer'image(to_integer(unsigned(shift_val)));
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assert (dout = vdout) report "[error] lsl. vdout = " & integer'image(to_integer(unsigned(vdout))) & " versus dout = " & integer'image(to_integer(unsigned(dout))) severity error;
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--assert (cout = vcout) report "[error] lsl. vcout = " & integer'image(to_integer(unsigned(vcout))) & " versus cout = " & integer'image(to_integer(unsigned(cout))) severity error;
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end loop la;
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wait for 1 ns;
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-- lsr
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report "lsr with 32 random values";
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shift_lsl <= '0';
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shift_lsr <= '1';
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la : for va in 0 to 31 loop
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uniform(seed1, seed2, x);
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y := integer(floor(x * 31.0)) + 1;
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shift_val <= std_logic_vector(to_unsigned(y, shift_val'length));
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uniform(seed1, seed2, x);
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y := integer(floor(x * 536870911.0));
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din <= std_logic_vector(to_unsigned(y, din'length));
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if (y mod 2) = 0 then
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cin <= '1';
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else
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cin <= '0';
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end if;
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wait for 1 ns;
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vdout := din ror shift_val;
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vcout := 0;
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report "din = " & integer'image(to_integer(unsigned(din)));
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report "shift_val = " & integer'image(to_integer(unsigned(shift_val)));
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assert (dout = vdout) report "[error] lsl. vdout = " & integer'image(to_integer(unsigned(vdout))) & " versus dout = " & integer'image(to_integer(unsigned(dout))) severity error;
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--assert (cout = vcout) report "[error] lsl. vcout = " & integer'image(to_integer(unsigned(vcout))) & " versus cout = " & integer'image(to_integer(unsigned(cout))) severity error;
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end loop la;
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wait for 1 ns;
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-- asr
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report "asr with 32 random values";
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shift_asr <= '1';
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shift_lsr <= '0';
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la : for va in 0 to 31 loop
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uniform(seed1, seed2, x);
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y := integer(floor(x * 31.0)) + 1;
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shift_val <= std_logic_vector(to_unsigned(y, shift_val'length));
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uniform(seed1, seed2, x);
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y := integer(floor(x * 536870911.0));
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din <= std_logic_vector(to_unsigned(y, din'length));
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if (y mod 2) = 0 then
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cin <= '1';
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else
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cin <= '0';
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end if;
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wait for 1 ns;
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vdout := din sra shift_val;
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vcout := 0;
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report "din = " & integer'image(to_integer(unsigned(din)));
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report "shift_val = " & integer'image(to_integer(unsigned(shift_val)));
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assert (dout = vdout) report "[error] lsl. vdout = " & integer'image(to_integer(unsigned(vdout))) & " versus dout = " & integer'image(to_integer(unsigned(dout))) severity error;
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--assert (cout = vcout) report "[error] lsl. vcout = " & integer'image(to_integer(unsigned(vcout))) & " versus cout = " & integer'image(to_integer(unsigned(cout))) severity error;
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end loop la;
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wait for 1 ns;
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-- ror
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report "ror with 32 random values";
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shift_ror <= '1';
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shift_asr <= '0';
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la : for va in 0 to 31 loop
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uniform(seed1, seed2, x);
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y := integer(floor(x * 31.0)) + 1;
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shift_val <= std_logic_vector(to_unsigned(y, shift_val'length));
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uniform(seed1, seed2, x);
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y := integer(floor(x * 536870911.0));
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din <= std_logic_vector(to_unsigned(y, din'length));
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if (y mod 2) = 0 then
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cin <= '1';
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else
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cin <= '0';
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end if;
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wait for 1 ns;
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vdout := din ror shift_val;
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vcout := 0;
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report "din = " & integer'image(to_integer(unsigned(din)));
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report "shift_val = " & integer'image(to_integer(unsigned(shift_val)));
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assert (dout = vdout) report "[error] lsl. vdout = " & integer'image(to_integer(unsigned(vdout))) & " versus dout = " & integer'image(to_integer(unsigned(dout))) severity error;
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--assert (cout = vcout) report "[error] lsl. vcout = " & integer'image(to_integer(unsigned(vcout))) & " versus cout = " & integer'image(to_integer(unsigned(cout))) severity error;
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end loop la;
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wait for 1 ns;
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-- rrx
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report "rrx with 32 random values";
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shift_rrx <= '1';
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shift_ror <= '0';
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la : for va in 0 to 31 loop
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uniform(seed1, seed2, x);
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y := integer(floor(x * 31.0)) + 1;
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shift_val <= std_logic_vector(to_unsigned(y, shift_val'length));
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uniform(seed1, seed2, x);
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y := integer(floor(x * 536870911.0));
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din <= std_logic_vector(to_unsigned(y, din'length));
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if (y mod 2) = 0 then
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cin <= '1';
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else
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cin <= '0';
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end if;
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wait for 1 ns;
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vdout := din rrx shift_val;
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vcout := 0;
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report "din = " & integer'image(to_integer(unsigned(din)));
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report "shift_val = " & integer'image(to_integer(unsigned(shift_val)));
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--assert (dout = vdout) report "[error] lsl. vdout = " & integer'image(to_integer(unsigned(vdout))) & " versus dout = " & integer'image(to_integer(unsigned(dout))) severity error;
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--assert (cout = vcout) report "[error] lsl. vcout = " & integer'image(to_integer(unsigned(vcout))) & " versus cout = " & integer'image(to_integer(unsigned(cout))) severity error;
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end loop la;
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wait for 1 ns;
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wait;
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end process;
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end Structurel;
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