131 lines
3.0 KiB
VHDL
131 lines
3.0 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity Reg is
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port(
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-- Write Port 1 prioritaire
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wdata1 : in Std_Logic_Vector(31 downto 0);
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wadr1 : in Std_Logic_Vector(3 downto 0);
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wen1 : in Std_Logic;
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-- Write Port 2 non prioritaire
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wdata2 : in Std_Logic_Vector(31 downto 0);
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wadr2 : in Std_Logic_Vector(3 downto 0);
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wen2 : in Std_Logic;
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-- Write CSPR Port
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wcry : in Std_Logic;
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wzero : in Std_Logic;
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wneg : in Std_Logic;
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wovr : in Std_Logic;
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cspr_wb : in Std_Logic;
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-- Read Port 1 32 bits
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reg_rd1 : out Std_Logic_Vector(31 downto 0);
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radr1 : in Std_Logic_Vector(3 downto 0);
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reg_v1 : out Std_Logic;
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-- Read Port 2 32 bits
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reg_rd2 : out Std_Logic_Vector(31 downto 0);
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radr2 : in Std_Logic_Vector(3 downto 0);
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reg_v2 : out Std_Logic;
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-- Read Port 3 32 bits
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reg_rd3 : out Std_Logic_Vector(31 downto 0);
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radr3 : in Std_Logic_Vector(3 downto 0);
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reg_v3 : out Std_Logic;
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-- read CSPR Port
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reg_cry : out Std_Logic;
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reg_zero : out Std_Logic;
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reg_neg : out Std_Logic;
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reg_ovr : out Std_Logic;
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reg_cznv : out Std_Logic;
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reg_vv : out Std_Logic;
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-- Invalidate Port
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inval_adr1 : in Std_Logic_Vector(3 downto 0);
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inval1 : in Std_Logic;
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inval_adr2 : in Std_Logic_Vector(3 downto 0);
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inval2 : in Std_Logic;
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inval_czn : in Std_Logic;
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inval_ovr : in Std_Logic;
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-- PC
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reg_pc : out Std_Logic_Vector(31 downto 0);
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reg_pcv : out Std_Logic;
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inc_pc : in Std_Logic;
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-- global interface
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ck : in Std_Logic;
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reset_n : in Std_Logic;
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vdd : in bit;
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vss : in bit);
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end Reg;
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architecture Behavior OF Reg is
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-- type representant un banc de taille 16
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-- contenant des registres de 32 bits;
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type lv32_array15 is array (0 to 15) of std_logic_vector(31 downto 0);
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-- register_bench(0 to 14) -> registre du processeur
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-- register_bench(15) -> pc
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signal register_bench : lv32_array15 := (others=>(others=>'0'));;
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-- bits de validite des registres
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signal register_bench_v : std_logic_vector(15 downto 0) := (others=>'0');
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signal reg_cznv_s : std_logic := '0';
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signal reg_vv_s : std_logic := '0';
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begin
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reg_logic: process(clk)
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begin
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if rising_edge(clk) then
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-- reset des bits de validité
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if (reset_n = '0') then
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-- au reset tous les registres sont consideres comme valides
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register_bench_v(15 donwto 0) <= (others => '1');
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-- TODO : les flags sont il valide aux resets ?
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else
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-- gestion de la validite
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register_bench_v(to_integer(unsigned(inval_adr1))) <= not inval1;
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register_bench_v(to_integer(unsigned(inval_adr1))) <= not inval2;
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reg_cznv_s <= not inval_czn;
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reg_vv_s <= not inval_ovr;
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reg_cznv <= reg_cznv_s;
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reg_vv <= reg_vv_s;
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if (reg_cznv = '0') then
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reg_cry <= wcry;
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reg_zero <= wzero;
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reg_neg <= wneg;
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else
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if (reg_vv = '0') then
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reg_ovr <= wovr;
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end if;
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end if;
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-- gestion de pc
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-- write
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-- read
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end if;
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end if;
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end process reg_logic;
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end Behavior;
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