projet-vlsi/reg_tb.vhdl

189 lines
5.2 KiB
VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.uniform;
use ieee.math_real.floor;
entity reg_tb is
end reg_tb;
architecture Structurel of reg_tb is
-- useful stuff
function bit_to_integer (s : std_logic) return integer is
begin
if s = '1' then
return 1;
else
return 0;
end if;
end function;
-- port 1 write priority
signal wdata1_tb : std_logic_vector(31 downto 0);
signal wadr1_tb : std_logic_vector(3 downto 0);
signal wen1_tb : std_logic;
-- port 2 write
signal wdata2_tb : std_logic_vector(31 downto 0);
signal wadr2_tb : std_logic_vector(3 downto 0);
signal wen2_tb : std_logic;
-- write cspr port
signal wcry_tb : std_logic; -- write c
signal wzero_tb : std_logic; -- write z
signal wneg_tb : std_logic; -- write n
signal wovr_tb : std_logic; -- write v
signal cspr_wb_tb : std_logic; -- write write back
-- read port 1 32 bits
signal reg_rd1_tb : std_logic_vector(31 downto 0);
signal radr1_tb : std_logic_vector(3 downto 0); --
signal reg_v1_tb : std_logic;
-- read port 2 32 bits
signal reg_rd2_tb : std_logic_vector(31 downto 0);
signal radr2_tb : std_logic_vector(3 downto 0);
signal reg_v2_tb : std_logic;
-- read port 3 32 bits
signal reg_rd3_tb : std_logic_vector(31 downto 0);
signal radr3_tb : std_logic_vector(3 downto 0);
signal reg_v3_tb : std_logic;
-- read cspr port
signal reg_cry_tb : std_logic;-- read c
signal reg_zero_tb : std_logic;-- read z
signal reg_neg_tb : std_logic;-- read n
signal reg_cznv_tb : std_logic;-- read czn validity
signal reg_ovr_tb : std_logic;-- read v
signal reg_vv_tb : std_logic;-- read v validity
-- invalidate port
signal inval_adr1_tb : std_logic_vector(3 downto 0);
signal inval1_tb : std_logic;
signal inval_adr2_tb : std_logic_vector(3 downto 0);
signal inval2_tb : std_logic;
signal inval_czn_tb : std_logic;
signal inval_ovr_tb : std_logic;
-- pc
signal reg_pc_tb : std_logic_vector(31 downto 0);
signal reg_pcv_tb : std_logic;
signal inc_pc_tb : std_logic;
-- global interface
signal ck_tb : std_logic;
signal reset_n_tb : std_logic;
signal vdd_tb : bit;
signal vss_tb : bit;
begin
reg_0 : entity work.reg(behavioral)
port map(
-- write port 1 priority
wdata1 => wdata1_tb;
wadr1 => wadr1_tb;
wen1 => wen1_tb;
-- write port 2
wdata2 => wdata2_tb;
wadr2 => wadr2_tb;
wen2 => wen2_tb;
-- write cspr port
wcry => wcry_tb;
wzero => wzero_tb;
wneg => wneg_tb;
wovr => wovr_tb;
cspr_wb => cspr_wb_tb;
-- read port 1 32 bits
reg_rd1 => reg_rd1_tb;
radr1 => radr1_tb;
reg_v1 => reg_v1_tb;
-- read port 2 32 bits
reg_rd2 => reg_rd2_tb;
radr2 => radr2_tb;
reg_rd1_tb
reg_v2 => reg_v2_tb;
-- read port 3 32 bits
reg_rd3 => reg_rd3_tb;
radr3 => radr3_tb;
reg_v3 => reg_v3_tb;
-- read cspr port
reg_cry => reg_cry_tb;
reg_zero => reg_zero_tb;
reg_neg => reg_neg_tb;
reg_cznv => reg_cznv_tb;
reg_ovr => reg_ovr_tb;
reg_vv => reg_vv_tb;
-- invalidate port
inval_adr1 => inval_adr1_tb;
inval1 => inval1_tb;
inval_adr2 => inval_adr2_tb;
inval2 => inval2_tb;
inval_czn => inval_czn_tb;
inval_ovr => inval_ovr_tb;
-- pc
reg_pc => reg_pc_tb;
reg_pcv => reg_pcv_tb;
inc_pc => inc_pc_tb;
-- global interface
ck => ck_tb;
reset_n => reset_n_tb;
vdd => vdd_tb;
vss => vss_tb
);
process
variable seed1 : positive;
variable seed2 : positive;
variable x : real;
variable y : integer;
begin
vdd_tb <= '1';
vss_tb <= '0';
reset_n_tb <= '1';
-- init clock
ck_tb <= '0';
-- set seeds for random number
seed1 := 1;
seed2 := 1;
wait for 1 ns;
reset_n_tb <= '0';
ck_tb <= '1';
wait for 1 ns;
for_registers : for i in 0 to 15 loop
radr1_tb <= std_logic_vector(to_unsigned(i, radr1_tb'length));
report "[debug] radr1_tb = " & integer'image(to_integer(unsigned(radr1_tb)));
radr2_tb <= std_logic_vector(to_unsigned(i, radr2_tb'length));
radr3_tb <= std_logic_vector(to_unsigned(i, radr3_tb'length));
end loop for_registers;
wait for 1 ns;
assert (bit_to_integer(v_tb) = bit_to_integer(vv)) report "reg_tb: [error] in v flag" severity error;
wait;
end process;
end structurel;