187 lines
5.1 KiB
VHDL
187 lines
5.1 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.uniform;
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use ieee.math_real.floor;
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entity reg_tb is
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end reg_tb;
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architecture Structurel of reg_tb is
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-- useful stuff
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function bit_to_integer (s : std_logic) return integer is
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begin
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if s = '1' then
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return 1;
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else
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return 0;
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end if;
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end function;
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-- port 1 write priority
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signal wdata1_tb : std_logic_vector(31 downto 0);
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signal wadr1_tb : std_logic_vector(3 downto 0);
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signal wen1_tb : std_logic;
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-- port 2 write
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signal wdata2_tb : std_logic_vector(31 downto 0);
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signal wadr2_tb : std_logic_vector(3 downto 0);
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signal wen2_tb : std_logic;
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-- write cspr port
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signal wcry_tb : std_logic; -- write c
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signal wzero_tb : std_logic; -- write z
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signal wneg_tb : std_logic; -- write n
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signal wovr_tb : std_logic; -- write v
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signal cspr_wb_tb : std_logic; -- write write back
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-- read port 1 32 bits
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signal reg_rd1_tb : std_logic_vector(31 downto 0);
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signal radr1_tb : std_logic_vector(3 downto 0); --
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signal reg_v1_tb : std_logic;
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-- read port 2 32 bits
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signal reg_rd2_tb : std_logic_vector(31 downto 0);
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signal radr2_tb : std_logic_vector(3 downto 0);
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signal reg_v2_tb : std_logic;
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-- read port 3 32 bits
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signal reg_rd3_tb : std_logic_vector(31 downto 0);
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signal radr3_tb : std_logic_vector(3 downto 0);
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signal reg_v3_tb : std_logic;
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-- read cspr port
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signal reg_cry_tb : std_logic;-- read c
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signal reg_zero_tb : std_logic;-- read z
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signal reg_neg_tb : std_logic;-- read n
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signal reg_cznv_tb : std_logic;-- read czn validity
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signal reg_ovr_tb : std_logic;-- read v
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signal reg_vv_tb : std_logic;-- read v validity
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-- invalidate port
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signal inval_adr1_tb : std_logic_vector(3 downto 0);
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signal inval1_tb : std_logic;
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signal inval_adr2_tb : std_logic_vector(3 downto 0);
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signal inval2_tb : std_logic;
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signal inval_czn_tb : std_logic;
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signal inval_ovr_tb : std_logic;
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-- pc
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signal reg_pc_tb : std_logic_vector(31 downto 0);
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signal reg_pcv_tb : std_logic;
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signal inc_pc_tb : std_logic;
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-- global interface
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signal ck_tb : std_logic;
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signal reset_n_tb : std_logic;
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signal vdd_tb : bit;
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signal vss_tb : bit;
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begin
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reg_0 : entity work.reg(behavioral)
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port map(
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-- write port 1 priority
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wdata1 => wdata1_tb;
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wadr1 => wadr1_tb;
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wen1 => wen1_tb;
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-- write port 2
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wdata2 => wdata2_tb;
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wadr2 => wadr2_tb;
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wen2 => wen2_tb;
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-- write cspr port
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wcry => wcry_tb;
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wzero => wzero_tb;
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wneg => wneg_tb;
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wovr => wovr_tb;
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cspr_wb => cspr_wb_tb;
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-- read port 1 32 bits
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reg_rd1 => reg_rd1_tb;
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radr1 => radr1_tb;
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reg_v1 => reg_v1_tb;
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-- read port 2 32 bits
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reg_rd2 => reg_rd2_tb;
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radr2 => radr2_tb;
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reg_rd1_tb
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reg_v2 => reg_v2_tb;
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-- read port 3 32 bits
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reg_rd3 => reg_rd3_tb;
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radr3 => radr3_tb;
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reg_v3 => reg_v3_tb;
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-- read cspr port
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reg_cry => reg_cry_tb;
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reg_zero => reg_zero_tb;
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reg_neg => reg_neg_tb;
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reg_cznv => reg_cznv_tb;
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reg_ovr => reg_ovr_tb;
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reg_vv => reg_vv_tb;
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-- invalidate port
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inval_adr1 => inval_adr1_tb;
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inval1 => inval1_tb;
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inval_adr2 => inval_adr2_tb;
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inval2 => inval2_tb;
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inval_czn => inval_czn_tb;
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inval_ovr => inval_ovr_tb;
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-- pc
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reg_pc => reg_pc_tb;
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reg_pcv => reg_pcv_tb;
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inc_pc => inc_pc_tb;
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-- global interface
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ck => ck_tb;
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reset_n => reset_n_tb;
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vdd => vdd_tb;
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vss => vss_tb
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);
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process
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variable seed1 : positive;
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variable seed2 : positive;
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variable x : real;
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variable y : integer;
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begin
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vdd_tb <= '1';
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vss_tb <= '0';
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reset_n_tb <= '1';
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-- init clock
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ck_tb <= '0';
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-- set seeds for random number
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seed1 := 1;
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seed2 := 1;
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wait for 1 ns;
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reset_n_tb <= '0';
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ck_tb <= '1';
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wait for 1 ns;
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for_registers : for i in 0 to 15 loop
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radr1_tb <= std_logic_vector(to_unsigned(i, radr1_tb'length));
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report "radr1_tb = " & integer'image(to_integer(unsigned(radr1_tb)));
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radr2_tb <= std_logic_vector(to_unsigned(i, radr2_tb'length));
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radr3_tb <= std_logic_vector(to_unsigned(i, radr3_tb'length));
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end loop for_registers;
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wait for 1 ns;
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wait;
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end process;
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end structurel;
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