380 lines
11 KiB
VHDL
380 lines
11 KiB
VHDL
library ieee;
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use ieee.math_real.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_1164.all;
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entity exec_tb is
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end exec_tb;
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architecture Structurel of exec_tb is
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signal dec2exe_empty : Std_logic;
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signal exe_pop : Std_logic;
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signal dec_op1 : Std_Logic_Vector(31 downto 0); -- first alu input
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signal dec_op2 : Std_Logic_Vector(31 downto 0); -- shifter input
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signal dec_exe_dest : Std_Logic_Vector(3 downto 0) ; -- Rd destination
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signal dec_exe_wb : Std_Logic; -- Rd destination write back
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signal dec_flag_wb : Std_Logic; -- CSPR modifiy
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signal dec_mem_data : Std_Logic_Vector(31 downto 0); -- data to MEM W
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signal dec_mem_dest : Std_Logic_Vector(3 downto 0) ; -- Destination MEM R
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signal dec_pre_index : Std_logic;
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signal dec_mem_lw : Std_Logic;
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signal dec_mem_lb : Std_Logic;
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signal dec_mem_sw : Std_Logic;
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signal dec_mem_sb : Std_Logic;
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signal dec_shift_lsl : Std_Logic;
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signal dec_shift_lsr : Std_Logic;
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signal dec_shift_asr : Std_Logic;
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signal dec_shift_ror : Std_Logic;
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signal dec_shift_rrx : Std_Logic;
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signal dec_shift_val : Std_Logic_Vector(4 downto 0);
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signal dec_cy : Std_Logic;
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signal dec_comp_op1 : Std_Logic;
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signal dec_comp_op2 : Std_Logic;
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signal dec_alu_cy : Std_Logic;
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signal dec_alu_cmd : Std_Logic_Vector(1 downto 0);
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signal exe_res : Std_Logic_Vector(31 downto 0);
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signal exe_c : Std_Logic;
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signal exe_v : Std_Logic;
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signal exe_n : Std_Logic;
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signal exe_z : Std_Logic;
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signal exe_dest : Std_Logic_Vector(3 downto 0); -- Rd destination
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signal exe_wb : Std_Logic; -- Rd destination write back
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signal exe_flag_wb : Std_Logic; -- CSPR modifiy
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signal exe_mem_adr : Std_Logic_Vector(31 downto 0); -- Alu res register
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signal exe_mem_data : Std_Logic_Vector(31 downto 0);
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signal exe_mem_dest : Std_Logic_Vector(3 downto 0);
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signal exe_mem_lw : Std_Logic;
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signal exe_mem_lb : Std_Logic;
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signal exe_mem_sw : Std_Logic;
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signal exe_mem_sb : Std_Logic;
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signal exe2mem_empty : Std_logic;
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signal mem_pop : Std_logic;
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signal ck : Std_logic := '0';
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signal reset_n : Std_logic;
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signal vdd : bit;
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signal vss : bit;
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begin
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ALU_ins: entity work.exec
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port map(
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dec2exe_empty => dec2exe_empty,
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exe_pop => exe_pop,
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dec_op1 => dec_op1,
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dec_op2 => dec_op2,
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dec_exe_dest => dec_exe_dest,
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dec_exe_wb => dec_exe_wb,
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dec_flag_wb => dec_flag_wb,
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dec_mem_data => dec_mem_data,
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dec_mem_dest => dec_mem_dest,
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dec_pre_index => dec_pre_index,
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dec_mem_lw => dec_mem_lw,
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dec_mem_lb => dec_mem_lb,
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dec_mem_sw => dec_mem_sw,
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dec_mem_sb => dec_mem_sb,
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dec_shift_lsl => dec_shift_lsl,
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dec_shift_lsr => dec_shift_lsr,
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dec_shift_asr => dec_shift_asr,
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dec_shift_ror => dec_shift_ror,
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dec_shift_rrx => dec_shift_rrx,
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dec_shift_val => dec_shift_val,
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dec_cy => dec_cy,
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dec_comp_op1 => dec_comp_op1,
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dec_comp_op2 => dec_comp_op2,
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dec_alu_cy => dec_alu_cy,
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dec_alu_cmd => dec_alu_cmd,
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exe_res => exe_res,
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exe_c => exe_c,
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exe_v => exe_v,
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exe_n => exe_n,
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exe_z => exe_z,
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exe_dest => exe_dest,
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exe_wb => exe_wb,
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exe_flag_wb => exe_flag_wb,
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exe_mem_adr => exe_mem_adr,
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exe_mem_data => exe_mem_data,
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exe_mem_dest => exe_mem_dest,
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exe_mem_lw => exe_mem_lw,
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exe_mem_lb => exe_mem_lb,
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exe_mem_sw => exe_mem_sw,
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exe_mem_sb => exe_mem_sb,
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exe2mem_empty => exe2mem_empty,
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mem_pop => mem_pop,
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ck => ck,
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reset_n => reset_n,
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vdd => vdd,
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vss => vss
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);
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-- HOLORGE
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ck <= not ck after 2 ns;
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process
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signal vexe_res : std_logic_vector(31 downto 0);
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begin
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-- decode interface synchro
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dec2exe_empty <= '0';
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-- decode interface operands
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dec_op1 <= x"00000005"; --important
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dec_op2 <= x"00000000"; --important
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dec_exe_dest <= x"1";
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dec_exe_wb <= '1';
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dec_flag_wb <= '1';
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-- decode to mem interface
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dec_mem_data <= x"00000000";
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dec_mem_dest <= x"2";
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dec_pre_index <= '1'; -- important
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dec_mem_lw <= '0';
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dec_mem_lb <= '0';
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dec_mem_sw <= '0';
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dec_mem_sb <= '0';
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--shifter command
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dec_shift_lsl <= '0';
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dec_shift_lsr <= '0';
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dec_shift_asr <= '0';
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dec_shift_ror <= '0';
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dec_shift_rrx <= '0';
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dec_shift_val <= "00000";
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dec_cy <= '0';
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-- Alu operand selection
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dec_comp_op1 <= '0';
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dec_comp_op2 <= '0';
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dec_alu_cy <= '0';
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-- alu command
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dec_alu_cmd <= "01";
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-- mem interface
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mem_pop <= '0';
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reset_n <= '1';
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vdd <= '1';
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vss <= '0';
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wait for 10 ns;
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-- add
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reset_n <= '0';
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dec_shift_lsl <= '0';
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dec_shift_lsr <= '0';
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dec_shift_asr <= '0';
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dec_shift_ror <= '0';
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dec_shift_rrx <= '0';
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dec_shift_val <= "00000";
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dec_alu_add <= '1';
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dec_alu_and <= '0';
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dec_alu_or <= '0';
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dec_alu_xor <= '0';
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dec_alu_cy <= '0';
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dec_comp_op1 <= '0';
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dec_comp_op2 <= '0';
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dec_op1 <= x"0000000F";
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dec_op2 <= x"0000000F";
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ck <= '1';
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wait for 10 ns;
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vexe_res <= x"0000001E";
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assert (exe_res = vexe_res) report "[error] vexe_res = " & integer'image(to_integer(unsigned(vexe_res))) & " versus exe_res = " & integer'image(to_integer(unsigned(exe_res))) severity error;
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-- add lsl
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dec_shift_lsl <= '1';
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dec_shift_lsr <= '0';
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dec_shift_asr <= '0';
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dec_shift_ror <= '0';
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dec_shift_rrx <= '0';
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dec_shift_val <= "00011";
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dec_alu_add <= '1';
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dec_alu_and <= '0';
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dec_alu_or <= '0';
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dec_alu_xor <= '0';
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dec_alu_cy <= '0';
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dec_comp_op1 <= '0';
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dec_comp_op2 <= '0';
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dec_op1 <= x"0000000F";
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dec_op2 <= x"000000E1";
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wait for 10 ns;
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vexe_res <= x"00000780";
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assert (exe_res = vexe_res) report "[error] vexe_res = " & integer'image(to_integer(unsigned(vexe_res))) & " versus exe_res = " & integer'image(to_integer(unsigned(exe_res))) severity error;
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-- and
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dec_shift_lsl <= '0';
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dec_shift_lsr <= '0';
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dec_shift_asr <= '0';
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dec_shift_ror <= '0';
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dec_shift_rrx <= '0';
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dec_shift_val <= "00000";
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dec_alu_add <= '0';
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dec_alu_and <= '1';
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dec_alu_or <= '0';
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dec_alu_xor <= '0';
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dec_alu_cy <= '0';
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dec_comp_op1 <= '0';
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dec_comp_op2 <= '0';
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dec_op1 <= x"01000001";
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dec_op2 <= x"01000000";
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wait for 10 ns;
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vexe_res <= x"01000000";
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assert (exe_res = vexe_res) report "[error] vexe_res = " & integer'image(to_integer(unsigned(vexe_res))) & " versus exe_res = " & integer'image(to_integer(unsigned(exe_res))) severity error;
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-- and lsr
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dec_shift_lsl <= '0';
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dec_shift_lsr <= '1';
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dec_shift_asr <= '0';
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dec_shift_ror <= '0';
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dec_shift_rrx <= '0';
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dec_shift_val <= "11111";
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dec_alu_add <= '0';
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dec_alu_and <= '1';
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dec_alu_or <= '0';
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dec_alu_xor <= '0';
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dec_alu_cy <= '0';
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dec_comp_op1 <= '0';
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dec_comp_op2 <= '0';
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dec_op1 <= x"01000001";
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dec_op2 <= x"FF000000";
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wait for 10 ns;
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vexe_res <= x"0000000";
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assert (exe_res = vexe_res) report "[error] vexe_res = " & integer'image(to_integer(unsigned(vexe_res))) & " versus exe_res = " & integer'image(to_integer(unsigned(exe_res))) severity error;
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-- mov
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dec_shift_lsl <= '0';
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dec_shift_lsr <= '0';
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dec_shift_asr <= '0';
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dec_shift_ror <= '0';
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dec_shift_rrx <= '0';
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dec_shift_val <= "00000";
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dec_alu_add <= '0';
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dec_alu_and <= '0';
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dec_alu_or <= '1';
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dec_alu_xor <= '0';
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dec_alu_cy <= '0';
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dec_comp_op1 <= '0';
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dec_comp_op2 <= '0';
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dec_zero_op1 <= '1';
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dec_op1 <= x"FFFFFFFF";
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dec_op2 <= x"12345678";
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wait for 10 ns;
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vexe_res <= x"FFFFFFFF";
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assert (exe_res = vexe_res) report "[error] vexe_res = " & integer'image(to_integer(unsigned(vexe_res))) & " versus exe_res = " & integer'image(to_integer(unsigned(exe_res))) severity error;
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-- or asr
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dec_shift_asr <= '1';
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dec_shift_val <= "00001";
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dec_op2 <= "1000" & x"0000002";
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wait for 2 ns;
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dec_shift_lsl <= '0';
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dec_shift_lsr <= '0';
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dec_shift_ror <= '0';
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dec_shift_rrx <= '0';
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dec_alu_add <= '0';
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dec_alu_and <= '0';
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dec_alu_or <= '1';
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dec_alu_xor <= '0';
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dec_alu_cy <= '0';
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dec_comp_op1 <= '0';
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dec_comp_op2 <= '0';
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dec_op1 <= x"01000001";
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wait for 10 ns;
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vexe_res <= x"08000000";
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assert (exe_res = vexe_res) report "[error] vexe_res = " & integer'image(to_integer(unsigned(vexe_res))) & " versus exe_res = " & integer'image(to_integer(unsigned(exe_res))) severity error;
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-- or
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dec_shift_lsl <= '0';
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dec_shift_lsr <= '0';
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dec_shift_asr <= '0';
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dec_shift_ror <= '0';
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dec_shift_rrx <= '0';
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dec_shift_val <= "00000";
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dec_alu_add <= '0';
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dec_alu_and <= '0';
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dec_alu_or <= '1';
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dec_alu_xor <= '0';
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dec_alu_cy <= '0';
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dec_comp_op1 <= '0';
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dec_comp_op2 <= '0';
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dec_op1 <= x"01000001";
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dec_op2 <= x"01000000";
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wait for 10 ns;
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vexe_res <= x"01000001";
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assert (exe_res = vexe_res) report "[error] vexe_res = " & integer'image(to_integer(unsigned(vexe_res))) & " versus exe_res = " & integer'image(to_integer(unsigned(exe_res))) severity error;
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-- xor
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dec_shift_lsl <= '0';
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dec_shift_lsr <= '0';
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dec_shift_asr <= '0';
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dec_shift_ror <= '0';
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dec_shift_rrx <= '0';
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dec_shift_val <= "00000";
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dec_alu_add <= '0';
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dec_alu_and <= '0';
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dec_alu_or <= '0';
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dec_alu_xor <= '1';
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dec_alu_cy <= '0';
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dec_comp_op1 <= '0';
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dec_comp_op2 <= '0';
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dec_op1 <= x"01000001";
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dec_op2 <= x"01000000";
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wait for 10 ns;
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vexe_res <= x"00000001";
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assert (exe_res = vexe_res) report "[error] vexe_res = " & integer'image(to_integer(unsigned(vexe_res))) & " versus exe_res = " & integer'image(to_integer(unsigned(exe_res))) severity error;
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end process;
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end Structurel;
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