projet-vlsi/adder32_tb.vhdl

79 lines
1.7 KiB
VHDL

library ieee;
use ieee.math_real.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
---
entity adder32_tb is
end adder32_tb;
---
architecture Structurel of adder32_tb is
-- component adder
-- port (
-- cin : IN std_logic;
-- i0, i1 : IN std_logic_vector(31 downto 0);
-- q : OUT std_logic_vector(31 downto 0);
-- cout : OUT std_logic
-- );
-- end component;
signal cout, cin : std_logic;
signal i0, i1, q_32 : std_logic_vector(31 downto 0);
signal vadd : std_logic_vector(31 downto 0);
impure function rand_int(min_val, max_val : integer) return integer is
variable r : real;
variable seed1, seed2 : integer := 998;
begin
uniform(seed1, seed2, r);
return integer(
round(r * real(max_val - min_val + 1) + real(min_val) - 0.5));
end function;
begin
adder_0: entity work.adder32_ent
port map(
cin => cin,
i0 => i0,
i1 => i1,
q => q_32,
cout => cout
);
process
variable rva, rvb : integer;
begin
cin <= '0';
loop_i0: for va in 0 to 15 loop
loop_i1: for vb in 0 to 15 loop
rva := rand_int(-200, 200);
rvb := rand_int(-200, 200);
i0 <= std_logic_vector(to_unsigned(va, 32));
i1 <= std_logic_vector(to_unsigned(vb, 32));
vadd <= std_logic_vector(to_unsigned(va+vb, 32));
wait for 2 fs;
report "i0 : " & integer'image(to_integer(unsigned(i0)))
& " + i1 : "
& integer'image(to_integer(unsigned(i1)))
& " = "
& integer'image(to_integer(unsigned(q_32)))
& " ( vadd = "
& integer'image(to_integer(unsigned(vadd)))
& " ) ";
assert vadd = q_32 report "ERROR not equal !" severity error;
end loop loop_i1;
end loop loop_i0;
wait;
end process;
end Structurel;