24 lines
418 B
VHDL
24 lines
418 B
VHDL
library ieee;
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use ieee.math_real.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_1164.all;
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-- ADDER 1 BIT
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----------------------------------------------------------------
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entity adder1_ent is
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port (
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i0, i1, cin : IN std_logic;
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q, cout : OUT std_logic
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);
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end entity;
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architecture adder1 of adder1_ent is
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begin
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q <= i0 xor i1 xor cin;
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cout <= (i0 and i1) or (i0 and cin) or (i1 and cin);
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end adder1;
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