library ieee;
use ieee.math_real.all;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;


-- ADDER 1 BIT
----------------------------------------------------------------
ENTITY adder1bit IS
PORT (
	i0, i1, cin 	: IN	std_logic;
	q, cout		: OUT	std_logic
);
END ENTITY;
-----------------------------------------------------------------
ARCHITECTURE full_adder_1bit OF adder1bit IS
BEGIN
	q 	<= i0 XOR i1 XOR cin;
	cout 	<= (i0 and i1) or (i0 and cin) or (i1 and cin);
END full_adder_1bit;