library ieee;
use ieee.math_real.all;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
--use work.adder1bit.all;

-----------------------------------------------------------------
-- ADDER 4 BIT
-----------------------------------------------------------------
ENTITY adder_4bit_ent IS
PORT (
	i0, i1	: IN	std_logic_vector(3 downto 0);
	q		: OUT	std_logic_vector(3 downto 0)
);
END ENTITY;
-----------------------------------------------------------------
ARCHITECTURE adder_4bit OF adder_4bit_ent IS

--COMPONENT adder1bit IS 
--PORT (
--	i0, i1, cin 	: IN	std_logic;
--	q, cout		: OUT	std_logic
--);
--END COMPONENT;

SIGNAL co : std_logic_vector(3 downto 0);

BEGIN
adder0 : entity work.adder1bit
PORT MAP (
	i0 => i0(0),
	i1 => i1(0),
	cin => '0',
	q  => q(0),
	cout => co(0)
);
loop_3: for i in 1 to 3 generate 
adderN : entity work.adder1bit
PORT MAP (
	i0 => i0(i),
	i1 => i1(i),
	cin => co(i-1),
	q  => q(i),
	cout => co(i)
);
END GENERATE loop_3;
END adder_4bit;