$date
  Wed Oct 27 12:29:22 2021
$end
$version
  GHDL v0
$end
$timescale
  1 fs
$end
$var reg 1 ! shift_lsl $end
$var reg 1 " shift_lsr $end
$var reg 1 # shift_asr $end
$var reg 1 $ shift_ror $end
$var reg 1 % shift_rrx $end
$var reg 5 & shift_val[4:0] $end
$var reg 32 ' din[31:0] $end
$var reg 1 ( cin $end
$var reg 32 ) dout[31:0] $end
$var reg 1 * cout $end
$var reg 1 + vdd $end
$var reg 1 , vss $end
$scope module shift $end
$var reg 1 - shift_lsl $end
$var reg 1 . shift_lsr $end
$var reg 1 / shift_asr $end
$var reg 1 0 shift_ror $end
$var reg 1 1 shift_rrx $end
$var reg 5 2 shift_val[4:0] $end
$var reg 32 3 din[31:0] $end
$var reg 1 4 cin $end
$var reg 32 5 dout[31:0] $end
$var reg 1 6 cout $end
$var reg 1 7 vdd $end
$var reg 1 8 vss $end
$upscope $end
$enddefinitions $end
#0
0!
0"
0#
1$
0%
b00010 &
b00000000000000000111111110001110 '
0(
b10000000000000000001111111100011 )
1*
1+
0,
0-
0.
0/
10
01
b00010 2
b00000000000000000111111110001110 3
04
b10000000000000000001111111100011 5
16
17
08
#5000000