library ieee;
use ieee.math_real.all;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;

entity ALU_tb is
end ALU_tb;


architecture Structurel of ALU_tb is
	signal op1	: std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(32654, 32));
	signal op2	: std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(65877, 32));
	signal cin	: std_logic := '0';
	signal cmd	: std_logic_vector(1 downto 0) := "00";
	signal res	: std_logic_vector(31 downto 0) := (others => '0');
	signal cout	: std_logic;
	signal z	: std_logic;
	signal n	: std_logic;
	signal v	: std_logic;
	signal vdd	: bit := '1';
	signal vss	: bit := '0';

begin


	ALU_ins: entity work.ALU
	port map(
		    op1 => op1,
		    op2 => op2,
		    cin => cin,
		    cmd => cmd,
		    res => res,
		    cout => cout,
		    z => z,
		    n => n,
		    v => v,
		    vdd => vdd,
		    vss => vss
		);

	process
	begin

		wait for 5 fs;
		cmd <= "00";
		wait for 5 fs;
		report "op1 = " & integer'image(to_integer(unsigned(op1)));
		report "op2 = " & integer'image(to_integer(unsigned(op2)));
		report "res = " & integer'image(to_integer(unsigned(res)));
		assert z/='1'report "z";
		assert n/='1'report "n";
		assert v/='1'report "v";

		wait for 5 fs;

		cmd <= "01";
		wait for 5 fs;
		report "op1 = " & integer'image(to_integer(unsigned(op1)));
		report "op2 = " & integer'image(to_integer(unsigned(op2)));
		report "res = " & integer'image(to_integer(unsigned(res)));
		assert z/='1'report "z";
		assert n/='1'report "n";
		assert v/='1'report "v";

		wait for 5 fs;

		cmd <= "10";
		wait for 5 fs;
		report "op1 = " & integer'image(to_integer(unsigned(op1)));
		report "op2 = " & integer'image(to_integer(unsigned(op2)));
		report "res = " & integer'image(to_integer(unsigned(res)));
		assert z/='1'report "z";
		assert n/='1'report "n";
		assert v/='1'report "v";

		wait for 5 fs;

		cmd <= "11";
		wait for 5 fs;
		report "op1 = " & integer'image(to_integer(unsigned(op1)));
		report "op2 = " & integer'image(to_integer(unsigned(op2)));
		report "res = " & integer'image(to_integer(unsigned(res)));
		assert z/='1'report "z";
		assert n/='1'report "n";
		assert v/='1'report "v";

		wait for 5 fs;
		cmd <= "00";
		wait for 5 fs;
		report "op1 = " & integer'image(to_integer(unsigned(op1)));
		report "op2 = " & integer'image(to_integer(unsigned(op2)));
		report "res = " & integer'image(to_integer(unsigned(res)));
		assert z/='1'report "z";
		assert n/='1'report "n";
		assert v/='1'report "v";


		wait for 5 fs;
		cmd <= "00";
		wait for 5 fs;
		report "op1 = " & integer'image(to_integer(unsigned(op1)));
		report "op2 = " & integer'image(to_integer(unsigned(op2)));
		report "res = " & integer'image(to_integer(unsigned(res)));
		assert z/='1'report "z";
		assert n/='1'report "n";
		assert v/='1'report "v";

		wait for 50 fs;

		wait;
	end process;

end Structurel;