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EXE tb

This commit is contained in:
Adrien Bourmault 2022-01-21 00:39:51 +01:00
parent ac26672bf8
commit ec3abab075
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GPG Key ID: 6EB408FE0ACEC664
2 changed files with 52 additions and 167 deletions
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217
exec_tb.vhdl
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@ -111,21 +111,53 @@ begin
-- HOLORGE -- HOLORGE
ck <= not ck after 2 ns; ck <= not ck after 2 ns;
process process
signal vexe_res : std_logic_vector(31 downto 0); signal vexe_res : std_logic_vector(31 downto 0);
begin begin
-- decode interface synchro
dec2exe_empty <= '0';
-- decode interface operands
dec_op1 <= x"00000005"; --important
dec_op2 <= x"00000000"; --important
dec_exe_dest <= x"1";
dec_exe_wb <= '1';
dec_flag_wb <= '1';
-- decode to mem interface
dec_mem_data <= x"00000000";
dec_mem_dest <= x"2";
dec_pre_index <= '1'; -- important
dec_mem_lw <= '0';
dec_mem_lb <= '0';
dec_mem_sw <= '0';
dec_mem_sb <= '0';
--shifter command
dec_shift_lsl <= '0';
dec_shift_lsr <= '0';
dec_shift_asr <= '0';
dec_shift_ror <= '0';
dec_shift_rrx <= '0';
dec_shift_val <= "00000";
dec_cy <= '0';
-- Alu operand selection
dec_comp_op1 <= '0';
dec_comp_op2 <= '0';
dec_alu_cy <= '0';
-- alu command
dec_alu_cmd <= "01";
-- mem interface
mem_pop <= '0';
reset_n <= '1';
vdd <= '1';
vss <= '0';
wait for 10 ns;
-- add -- add
ck <= '0';
wait for 2 ns;
reset_n <= '0'; reset_n <= '0';
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
dec_shift_lsl <= '0'; dec_shift_lsl <= '0';
dec_shift_lsr <= '0'; dec_shift_lsr <= '0';
@ -148,30 +180,12 @@ begin
dec_op2 <= x"0000000F"; dec_op2 <= x"0000000F";
ck <= '1'; ck <= '1';
wait for 2 ns; wait for 10 ns;
ck <= '0';
wait for 2 ns;
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
ck <= '1';
wait;
vexe_res <= x"0000001E"; vexe_res <= x"0000001E";
assert (exe_res = vexe_res) report "[error] vexe_res = " & integer'image(to_integer(unsigned(vexe_res))) & " versus exe_res = " & integer'image(to_integer(unsigned(exe_res))) severity error; assert (exe_res = vexe_res) report "[error] vexe_res = " & integer'image(to_integer(unsigned(vexe_res))) & " versus exe_res = " & integer'image(to_integer(unsigned(exe_res))) severity error;
-- add lsl -- add lsl
ck <= '0';
wait for 2 ns;
reset_n <= '0';
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
dec_shift_lsl <= '1'; dec_shift_lsl <= '1';
dec_shift_lsr <= '0'; dec_shift_lsr <= '0';
dec_shift_asr <= '0'; dec_shift_asr <= '0';
@ -191,32 +205,12 @@ begin
dec_op1 <= x"0000000F"; dec_op1 <= x"0000000F";
dec_op2 <= x"000000E1"; dec_op2 <= x"000000E1";
ck <= '1'; wait for 10 ns;
wait for 2 ns;
ck <= '0';
wait for 2 ns;
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
ck <= '1';
wait;
vexe_res <= x"00000780"; vexe_res <= x"00000780";
assert (exe_res = vexe_res) report "[error] vexe_res = " & integer'image(to_integer(unsigned(vexe_res))) & " versus exe_res = " & integer'image(to_integer(unsigned(exe_res))) severity error; assert (exe_res = vexe_res) report "[error] vexe_res = " & integer'image(to_integer(unsigned(vexe_res))) & " versus exe_res = " & integer'image(to_integer(unsigned(exe_res))) severity error;
-- and -- and
ck <= '0';
wait for 2 ns;
reset_n <= '0';
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
dec_shift_lsl <= '0'; dec_shift_lsl <= '0';
dec_shift_lsr <= '0'; dec_shift_lsr <= '0';
dec_shift_asr <= '0'; dec_shift_asr <= '0';
@ -236,33 +230,13 @@ begin
dec_op1 <= x"01000001"; dec_op1 <= x"01000001";
dec_op2 <= x"01000000"; dec_op2 <= x"01000000";
ck <= '1'; wait for 10 ns;
wait for 2 ns;
ck <= '0';
wait for 2 ns;
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
ck <= '1';
wait;
vexe_res <= x"01000000"; vexe_res <= x"01000000";
assert (exe_res = vexe_res) report "[error] vexe_res = " & integer'image(to_integer(unsigned(vexe_res))) & " versus exe_res = " & integer'image(to_integer(unsigned(exe_res))) severity error; assert (exe_res = vexe_res) report "[error] vexe_res = " & integer'image(to_integer(unsigned(vexe_res))) & " versus exe_res = " & integer'image(to_integer(unsigned(exe_res))) severity error;
-- and lsr -- and lsr
ck <= '0';
wait for 2 ns;
reset_n <= '0';
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
dec_shift_lsl <= '0'; dec_shift_lsl <= '0';
dec_shift_lsr <= '1'; dec_shift_lsr <= '1';
dec_shift_asr <= '0'; dec_shift_asr <= '0';
@ -282,33 +256,13 @@ begin
dec_op1 <= x"01000001"; dec_op1 <= x"01000001";
dec_op2 <= x"FF000000"; dec_op2 <= x"FF000000";
ck <= '1'; wait for 10 ns;
wait for 2 ns;
ck <= '0';
wait for 2 ns;
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
ck <= '1';
wait;
vexe_res <= x"0000000"; vexe_res <= x"0000000";
assert (exe_res = vexe_res) report "[error] vexe_res = " & integer'image(to_integer(unsigned(vexe_res))) & " versus exe_res = " & integer'image(to_integer(unsigned(exe_res))) severity error; assert (exe_res = vexe_res) report "[error] vexe_res = " & integer'image(to_integer(unsigned(vexe_res))) & " versus exe_res = " & integer'image(to_integer(unsigned(exe_res))) severity error;
-- mov -- mov
ck <= '0';
wait for 2 ns;
reset_n <= '0';
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
dec_shift_lsl <= '0'; dec_shift_lsl <= '0';
dec_shift_lsr <= '0'; dec_shift_lsr <= '0';
dec_shift_asr <= '0'; dec_shift_asr <= '0';
@ -330,36 +284,19 @@ begin
dec_op1 <= x"FFFFFFFF"; dec_op1 <= x"FFFFFFFF";
dec_op2 <= x"12345678"; dec_op2 <= x"12345678";
ck <= '1'; wait for 10 ns;
wait for 2 ns;
ck <= '0';
wait for 2 ns;
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
ck <= '1';
wait;
vexe_res <= x"FFFFFFFF"; vexe_res <= x"FFFFFFFF";
assert (exe_res = vexe_res) report "[error] vexe_res = " & integer'image(to_integer(unsigned(vexe_res))) & " versus exe_res = " & integer'image(to_integer(unsigned(exe_res))) severity error; assert (exe_res = vexe_res) report "[error] vexe_res = " & integer'image(to_integer(unsigned(vexe_res))) & " versus exe_res = " & integer'image(to_integer(unsigned(exe_res))) severity error;
-- or asr -- or asr
ck <= '0';
wait for 2 ns;
reset_n <= '0';
ck <= '1';
wait for 2 ns;
dec_shift_asr <= '1'; dec_shift_asr <= '1';
dec_shift_val <= "00001"; dec_shift_val <= "00001";
dec_op2 <= "1000" & x"0000002"; dec_op2 <= "1000" & x"0000002";
ck <= '0';
wait for 2 ns; wait for 2 ns;
dec_shift_lsl <= '0'; dec_shift_lsl <= '0';
@ -380,33 +317,13 @@ begin
dec_op1 <= x"01000001"; dec_op1 <= x"01000001";
ck <= '1'; wait for 10 ns;
wait for 2 ns;
ck <= '0';
wait for 2 ns;
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
ck <= '1';
wait;
vexe_res <= x"08000000"; vexe_res <= x"08000000";
assert (exe_res = vexe_res) report "[error] vexe_res = " & integer'image(to_integer(unsigned(vexe_res))) & " versus exe_res = " & integer'image(to_integer(unsigned(exe_res))) severity error; assert (exe_res = vexe_res) report "[error] vexe_res = " & integer'image(to_integer(unsigned(vexe_res))) & " versus exe_res = " & integer'image(to_integer(unsigned(exe_res))) severity error;
-- or -- or
ck <= '0';
wait for 2 ns;
reset_n <= '0';
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
dec_shift_lsl <= '0'; dec_shift_lsl <= '0';
dec_shift_lsr <= '0'; dec_shift_lsr <= '0';
dec_shift_asr <= '0'; dec_shift_asr <= '0';
@ -426,33 +343,13 @@ begin
dec_op1 <= x"01000001"; dec_op1 <= x"01000001";
dec_op2 <= x"01000000"; dec_op2 <= x"01000000";
ck <= '1'; wait for 10 ns;
wait for 2 ns;
ck <= '0';
wait for 2 ns;
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
ck <= '1';
wait;
vexe_res <= x"01000001"; vexe_res <= x"01000001";
assert (exe_res = vexe_res) report "[error] vexe_res = " & integer'image(to_integer(unsigned(vexe_res))) & " versus exe_res = " & integer'image(to_integer(unsigned(exe_res))) severity error; assert (exe_res = vexe_res) report "[error] vexe_res = " & integer'image(to_integer(unsigned(vexe_res))) & " versus exe_res = " & integer'image(to_integer(unsigned(exe_res))) severity error;
-- xor -- xor
ck <= '0';
wait for 2 ns;
reset_n <= '0';
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
dec_shift_lsl <= '0'; dec_shift_lsl <= '0';
dec_shift_lsr <= '0'; dec_shift_lsr <= '0';
dec_shift_asr <= '0'; dec_shift_asr <= '0';
@ -472,21 +369,11 @@ begin
dec_op1 <= x"01000001"; dec_op1 <= x"01000001";
dec_op2 <= x"01000000"; dec_op2 <= x"01000000";
ck <= '1'; wait for 10 ns;
wait for 2 ns;
ck <= '0';
wait for 2 ns;
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
ck <= '1';
wait;
vexe_res <= x"00000001"; vexe_res <= x"00000001";
assert (exe_res = vexe_res) report "[error] vexe_res = " & integer'image(to_integer(unsigned(vexe_res))) & " versus exe_res = " & integer'image(to_integer(unsigned(exe_res))) severity error; assert (exe_res = vexe_res) report "[error] vexe_res = " & integer'image(to_integer(unsigned(vexe_res))) & " versus exe_res = " & integer'image(to_integer(unsigned(exe_res))) severity error;
end process; end process;
end Structurel; end Structurel;

2
reg_tb.vhdl
View File

@ -180,8 +180,6 @@ begin
wait for 1 ns; wait for 1 ns;
assert (bit_to_integer(v_tb) = bit_to_integer(vv)) report "reg_tb: [error] in v flag" severity error;
wait; wait;
end process; end process;
end structurel; end structurel;