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Shifter_tb WIP

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Adrien Bourmault 2021-12-23 17:35:49 +01:00
parent 1beb63f3ce
commit e8f3e33271
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GPG Key ID: 6EB408FE0ACEC664
1 changed files with 57 additions and 6 deletions
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63
shifter_tb.vhdl
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@ -19,6 +19,7 @@ signal dout : Std_Logic_Vector(31 downto 0);
signal cout : Std_Logic;
signal vdd : bit := '1';
signal vss : bit := '0';
begin
shift: entity work.Shifter
@ -37,13 +38,63 @@ port map(
vss => vss
);
process
-- Variables for the random number
variable seed1 : positive;
variable seed2 : positive;
variable x : real;
variable y : integer;
variable vdout : std_logic_vector(31 downto 0);
variable vcout : std_logic;
begin
shift_ror <= '1';
shift_val <= "00010";
din <= std_logic_vector(to_unsigned(32654, 32));
wait for 5 ns;
report "dout = " & integer'image(to_integer(unsigned(dout)));
WAIT;
-- set vdd to 5v
vdd <= '1';
-- set vss to gnd
vss <= '0';
-- seeds for random number
seed1 := 1;
seed2 := 1;
wait for 1 ns;
report "[test_01] lsl with 32 random values";
shift_lsl <= '1';
la : for va in 0 to 31 loop
uniform(seed1, seed2, x);
y := integer(floor(x * 31.0)) + 1;
shift_val <= std_logic_vector(to_unsigned(y, shift_val'length));
uniform(seed1, seed2, x);
y := integer(floor(x * 536870911.0));
din <= std_logic_vector(to_unsigned(y, din'length));
if (y mod 2) = 0 then
cin <= '1';
else
cin <= '0';
end if;
wait for 1 ns;
--vdout := ?
--vcout := ?
report "[test_01]: din = " & integer'image(to_integer(unsigned(din)));
report "[test_01]: shift_val = " & integer'image(to_integer(unsigned(shift_val)));
assert (dout = vdout) report "[error] lsl. vdout = " & integer'image(to_integer(unsigned(vdout))) & " versus dout = " & integer'image(to_integer(unsigned(dout))) severity error;
assert (cout = vcout) report "[error] lsl. vcout = " & integer'image(to_integer(unsigned(vcout))) & " versus cout = " & integer'image(to_integer(unsigned(cout))) severity error;
end loop la;
report "[test_01] finished";
wait for 1 ns;
assert false report "end_of_test" severity note;
-- wait forever; this will finish the simulation.
wait;
end process;
end Structurel;