ALU testbench
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Adrien Bourmault
parent
14b2bcf4a2
commit
d983073bec
348
alu_tb.vhdl
348
alu_tb.vhdl
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@ -3,12 +3,14 @@ use ieee.math_real.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_1164.all;
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entity ALU_tb is
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end ALU_tb;
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entity ALU is
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end ALU;
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architecture Structurel of ALU is
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architecture Structurel of ALU_tb is
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signal op1 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(32654, 32));
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--! ######## signals for component ########
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signal op1 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(32654, 32));
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signal op2 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(65877, 32));
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signal cin : std_logic := '0';
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signal cmd : std_logic_vector(1 downto 0) := "00";
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@ -20,94 +22,266 @@ architecture Structurel of ALU_tb is
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signal vdd : bit := '1';
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signal vss : bit := '0';
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--! ######## functions ########
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function bit_to_integer (s : std_logic) return integer is
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begin
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if s = '1' then
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return 1;
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else
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return 0;
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end if;
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end function;
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begin
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alu_0 : entity work.alu(behavioral)
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port map(
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op1 => op1,
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op2 => op2,
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res => res,
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cin => cin,
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cout => cout,
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z => z,
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n => n,
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v => v,
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cmd => cmd,
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vdd => vdd,
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vss => vss
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);
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process
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variable vres : std_logic_vector(31 downto 0);
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variable vtempcin : natural;
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variable vtemp : std_logic_vector(32 downto 0);
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variable vcarry_out : std_logic;
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variable vz : std_logic;
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variable vv : std_logic;
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-- variables for the random number
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variable seed1 : positive;
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variable seed2 : positive;
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variable x : real;
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variable y : integer;
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begin
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vdd <= '1';
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vss <= '0';
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-- seeds for random number
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seed1 := 1;
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seed2 := 1;
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cin <= '1';
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vtempcin := 0;
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wait for 1 ns;
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-- SUM
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cmd <= "00";
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wait for 1 ns;
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report "[test_01] addition of 32 random numbers, range between (0 to 536870911)";
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la : for va in 0 to 31 loop
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-- calcul the first random number
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uniform(seed1, seed2, x);
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y := integer(floor(x * 536870911.0));
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-- assign the random number to op1
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op1 <= std_logic_vector(to_unsigned(y, op1'length));
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-- calcul the second random number
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uniform(seed1, seed2, x);
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y := integer(floor(x * 536870911.0));
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-- assign the random number to op2
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op2 <= std_logic_vector(to_unsigned(y, op2'length));
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wait for 1 ns;
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vtemp := (std_logic_vector(unsigned("0" & op1) + unsigned("0" & op2) + to_unsigned(bit_to_integer(cin), 1)));
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vres := vtemp(31 downto 0);
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vcarry_out := vtemp(32);
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if vres = x"0" then
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vz := '1';
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else
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vz := '0';
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end if;
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wait for 1 ns;
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assert (res = vres) report "[error] resultat of sum. vres = " & integer'image(to_integer(unsigned(vres))) & " versus res = " & integer'image(to_integer(unsigned(res)))
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severity error;
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assert (bit_to_integer(n) = bit_to_integer(vtemp(31))) report "[error] negative. n = " & integer'image(bit_to_integer(n)) & " versus vn = " & integer'image(bit_to_integer(vtemp(31)))
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severity error;
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assert (bit_to_integer(cout) = bit_to_integer(vtemp(32))) report "[error] in carry out. cout = " & integer'image(bit_to_integer(cout)) & " versus vcout = " & integer'image(bit_to_integer(vtemp(32)))
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severity error;
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assert (bit_to_integer(z) = bit_to_integer(vz)) report "[error] z flag. z = " & integer'image(bit_to_integer(z)) & " versus vz = " & integer'image(bit_to_integer(vz))
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severity error;
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end loop la;
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report "[test_01] finished";
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ALU_ins: entity work.ALU
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port map(
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op1 => op1,
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op2 => op2,
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cin => cin,
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cmd => cmd,
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res => res,
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cout => cout,
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z => z,
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n => n,
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v => v,
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vdd => vdd,
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vss => vss
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);
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process
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begin
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wait for 5 fs;
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cmd <= "00";
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wait for 5 fs;
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report "op1 = " & integer'image(to_integer(unsigned(op1)));
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report "op2 = " & integer'image(to_integer(unsigned(op2)));
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report "res = " & integer'image(to_integer(unsigned(res)));
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assert z/='1'report "z";
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assert n/='1'report "n";
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assert v/='1'report "v";
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wait for 5 fs;
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cmd <= "01";
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wait for 5 fs;
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report "op1 = " & integer'image(to_integer(unsigned(op1)));
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report "op2 = " & integer'image(to_integer(unsigned(op2)));
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report "res = " & integer'image(to_integer(unsigned(res)));
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assert z/='1'report "z";
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assert n/='1'report "n";
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assert v/='1'report "v";
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wait for 5 fs;
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cmd <= "10";
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wait for 5 fs;
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report "op1 = " & integer'image(to_integer(unsigned(op1)));
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report "op2 = " & integer'image(to_integer(unsigned(op2)));
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report "res = " & integer'image(to_integer(unsigned(res)));
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assert z/='1'report "z";
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assert n/='1'report "n";
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assert v/='1'report "v";
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wait for 5 fs;
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cmd <= "11";
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wait for 5 fs;
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report "op1 = " & integer'image(to_integer(unsigned(op1)));
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report "op2 = " & integer'image(to_integer(unsigned(op2)));
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report "res = " & integer'image(to_integer(unsigned(res)));
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assert z/='1'report "z";
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assert n/='1'report "n";
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assert v/='1'report "v";
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wait for 5 fs;
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cmd <= "00";
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wait for 5 fs;
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report "op1 = " & integer'image(to_integer(unsigned(op1)));
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report "op2 = " & integer'image(to_integer(unsigned(op2)));
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report "res = " & integer'image(to_integer(unsigned(res)));
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assert z/='1'report "z";
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assert n/='1'report "n";
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assert v/='1'report "v";
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cin <= '0';
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wait for 1 ns;
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report "[test_02] addition of (7fff ffff) + (7fff ffff)";
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op1 <= x"7fffffff"; --(+)2147483647
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op2 <= x"7fffffff"; --(+)2147483647
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wait for 1 ns;
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assert (res = x"fffffffe") report "[error] res = " & integer'image(to_integer(unsigned(res))) severity error;
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assert (bit_to_integer(cout) = 0) report "cout = " & integer'image(bit_to_integer(cout)) severity error;
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assert (bit_to_integer(v) = 1) report "[error] v = " & integer'image(bit_to_integer(v)) severity error;
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report "[test_02] finished";
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wait for 5 fs;
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cmd <= "00";
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wait for 5 fs;
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report "op1 = " & integer'image(to_integer(unsigned(op1)));
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report "op2 = " & integer'image(to_integer(unsigned(op2)));
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report "res = " & integer'image(to_integer(unsigned(res)));
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assert z/='1'report "z";
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assert n/='1'report "n";
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assert v/='1'report "v";
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wait for 1 ns;
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report "[test_03] test overflow, zero and carry in addition (ffff ffff) + (0000 0001)";
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op1 <= x"ffffffff";
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op2 <= x"00000001";
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wait for 1 ns;
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assert (res = x"00000000") report "[error] res = " & integer'image(to_integer(unsigned(res))) severity error;
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assert (bit_to_integer(z) = 1) report "[error] z = " & integer'image(bit_to_integer(z)) severity error;
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assert (bit_to_integer(cout) = 1) report "[error] cout = " & integer'image(bit_to_integer(cout)) severity error;
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assert (bit_to_integer(v) = 1) report "[error] v = " & integer'image(bit_to_integer(v)) severity error;
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report "[test_03] finished";
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wait for 50 fs;
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wait;
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end process;
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wait for 1 ns;
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report "[test_04] test addition negative number with negative result";
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op1 <= x"0000002a"; -- 42
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op2 <= x"ffffffd3"; -- -45
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wait for 1 ns;
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assert (res = x"fffffffd") report "[error] res = " & integer'image(to_integer(unsigned(res))) severity error;
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assert (bit_to_integer(n) = 1) report "[error] n = " & integer'image(bit_to_integer(n)) severity error;
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assert (bit_to_integer(z) = 0) report "[error] z = " & integer'image(bit_to_integer(z)) severity error;
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assert (bit_to_integer(cout) = 0) report "[error] cout = " & integer'image(bit_to_integer(cout)) severity error;
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assert (bit_to_integer(v) = 1) report "[error] v = " & integer'image(bit_to_integer(v)) severity error;
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report "[test_04] finished";
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end Structurel;
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-- AND
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wait for 1 ns;
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report "[test_05] and of 32 random numbers in a range between (0 to 536870911)";
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cmd <= "01";
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wait for 1 ns;
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lb : for vb in 0 to 31 loop
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uniform(seed1, seed2, x);
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y := integer(floor(x * 536870911.0));
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op1 <= std_logic_vector(to_unsigned(y, op1'length));
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uniform(seed1, seed2, x);
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y := integer(floor(x * 536870911.0));
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op2 <= std_logic_vector(to_unsigned(y, op2'length));
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wait for 1 ns;
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vtemp := (("0" & op1) and ("0" & op2));
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vres := vtemp(31 downto 0);
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vcarry_out := vtemp(32);
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if vres = x"0" then
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vz := '1';
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else
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vz := '0';
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end if;
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wait for 1 ns;
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assert (res = vres) report "[error] or vres = " & integer'image(to_integer(unsigned(vres))) & " versus res = " & integer'image(to_integer(unsigned(res)))
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severity error;
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assert (bit_to_integer(n) = bit_to_integer(vtemp(31))) report "[error] negative. n = " & integer'image(bit_to_integer(n)) & " versus vn = " & integer'image(bit_to_integer(vtemp(32)))
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severity error;
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assert (bit_to_integer(cout) = bit_to_integer(vtemp(32))) report "[error] carry out. cout = " & integer'image(bit_to_integer(cout)) & " versus vcout = " & integer'image(bit_to_integer(vtemp(32)))
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severity error;
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assert (bit_to_integer(z) = bit_to_integer(vz)) report "[error] z flag. z = " & integer'image(bit_to_integer(z)) & " versus vz = " & integer'image(bit_to_integer(vz))
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severity error;
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end loop lb;
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report "[test_05] finished";
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-- OR
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wait for 1 ns;
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report "[test_06] or of 32 random numbers in a range between (0 to 536870911)";
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cmd <= "10";
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wait for 1 ns;
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lc : for vc in 0 to 31 loop
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-- calcul the first random number
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uniform(seed1, seed2, x);
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y := integer(floor(x * 536870911.0));
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-- assign the random number to op1
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op1 <= std_logic_vector(to_unsigned(y, op1'length));
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-- calcul the second random number
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uniform(seed1, seed2, x);
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y := integer(floor(x * 536870911.0));
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-- assign the random number to op2
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op2 <= std_logic_vector(to_unsigned(y, op2'length));
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wait for 1 ns;
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vtemp := (("0" & op1) or ("0" & op2));
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vres := vtemp(31 downto 0);
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vcarry_out := vtemp(32);
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if vres = x"0" then
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vz := '1';
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else
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vz := '0';
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end if;
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wait for 1 ns;
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assert (res = vres) report "[error] or vres = " & integer'image(to_integer(unsigned(vres))) & " res = " & integer'image(to_integer(unsigned(res)))
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severity error;
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assert (bit_to_integer(n) = bit_to_integer(vtemp(31))) report "[error] negative. n = " & integer'image(bit_to_integer(n)) & " versus vn = " & integer'image(bit_to_integer(vtemp(32)))
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severity error;
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assert (bit_to_integer(cout) = bit_to_integer(vtemp(32))) report "[error] carry out. cout = " & integer'image(bit_to_integer(cout)) & " versus cout = " & integer'image(bit_to_integer(vtemp(32)))
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severity error;
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assert (bit_to_integer(z) = bit_to_integer(vz)) report "[error] z flag. z = " & integer'image(bit_to_integer(z)) & " versus vz = " & integer'image(bit_to_integer(vz))
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severity error;
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end loop lc;
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report "[test_06] finished";
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-- XOR
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wait for 1 ns;
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report "[test_07] xor of 32 random numbers in a range between (0 to 536870911)";
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cmd <= "11";
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wait for 1 ns;
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ld : for vd in 0 to 31 loop
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-- calcul the first random number
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uniform(seed1, seed2, x);
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y := integer(floor(x * 536870911.0));
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-- assign the random number to op1
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op1 <= std_logic_vector(to_unsigned(y, op1'length));
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-- calcul the second random number
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uniform(seed1, seed2, x);
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y := integer(floor(x * 536870911.0));
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-- assign the random number to op2
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op2 <= std_logic_vector(to_unsigned(y, op2'length));
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wait for 1 ns;
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vtemp := (("0" & op1) xor ("0" & op2));
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vres := vtemp(31 downto 0);
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vcarry_out := vtemp(32);
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if vres = x"0" then
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vz := '1';
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else
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vz := '0';
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end if;
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wait for 1 ns;
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assert (res = vres) report "[error] xor. vres = " & integer'image(to_integer(unsigned(vres))) & " versus res = " & integer'image(to_integer(unsigned(res)))
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severity error;
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assert (bit_to_integer(n) = bit_to_integer(vtemp(31))) report "[error] negative. n = " & integer'image(bit_to_integer(n)) & " versus vn = " & integer'image(bit_to_integer(vtemp(32)))
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severity error;
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assert (bit_to_integer(cout) = bit_to_integer(vtemp(32))) report "[error] carry out. cout = " & integer'image(bit_to_integer(cout)) & " versus vcout = " & integer'image(bit_to_integer(vtemp(32)))
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severity error;
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assert (bit_to_integer(z) = bit_to_integer(vz)) report "[error] z flag. z = " & integer'image(bit_to_integer(z)) & " versus vz = " & integer'image(bit_to_integer(vz))
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severity error;
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end loop ld;
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report "[test_07] finished";
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wait for 1 ns;
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assert false report "end_of_test" severity note;
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wait;
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end process;
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end structurel;
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