Makefile now clean

Makefile

@@ -1,45 +1,20 @@
 GHDL = ghdl
-all : adder32_tb
+all : sim_alu #sim_shifter
 
-# %.o : %.vhdl
-# 	${GHDL} -a -g -v $^
-
-adder1.o : adder1.vhdl
-	${GHDL} -a -v adder1.vhdl
-
-adder32.o : adder32.vhdl adder1.o
-	${GHDL} -a -v adder32.vhdl
-
-adder32_tb.o : adder32_tb.vhdl adder32.o
-	${GHDL} -a -v adder32_tb.vhdl
+%.o : %.vhdl
+	${GHDL} -a -g -v $^
 
 adder32_tb : adder1.o adder32.o adder32_tb.o
 	${GHDL} -e -v adder32_tb
 
-
-shifter.o : shifter.vhdl
-	${GHDL} -a -v shifter.vhdl
-
-shifter_tb.o : shitfter_tb.vhdl shifter.o
-	${GHDL} -a -v shifter_tb.vhdl
-
 shifter_tb : shitfter.o shitfter_tb.o
 	${GHDL} -e -v shifter_tb
 
-
-
-alu.o : alu.vhdl adder32.o
-	${GHDL} -a -v alu.vhdl
-
-alu_tb.o : alu_tb.vhdl alu.o
-	${GHDL} -a -v alu_tb.vhdl
-
 alu_tb : adder1.o adder32.o alu.o alu_tb.o
 	${GHDL} -e -v alu_tb
 
-
 sim_adder32 : adder32_tb
-	${GHDL} -r adder_32bit_tb --vcd=alu.vcd
+	${GHDL} -r adder32_tb --vcd=adder32.vcd
 
 sim_alu : alu_tb
 	${GHDL} -r alu_tb --vcd=alu.vcd

adder32.vhdl

@@ -22,7 +22,7 @@ architecture adder32 of adder32_ent is
 	signal co : std_logic_vector(31 downto 0);
 
 begin
-	adder32_0 : entity work.adder1
+	adder32_0 : entity work.adder1_ent
 		port map (
 			i0	=> i0(0),
 			i1	=> i1(0),
@@ -33,7 +33,7 @@ begin
 
 	loop_29: for i in 1 to 30 generate
 
-	adder32_n : entity work.adder1
+	adder32_n : entity work.adder1_ent
 		port map (
 			i0	=> i0(i),
 			i1	=> i1(i),
@@ -43,7 +43,7 @@ begin
 		);
 	end generate loop_29;
 
-	adder32_31 : entity work.adder1
+	adder32_31 : entity work.adder1_ent
 		port map (
 			i0	=> i0(31),
 			i1	=> i1(31),

work-obj93.cf

@@ -1,4 +0,0 @@
-v 4
-file . "adder1.vhdl" "a49b2e44f386a417daff4e60add5fa1c51cd5e86" "20211027090651.627":
-  entity adder1_ent at 1( 0) + 0 on 23;
-  architecture adder1 of adder1_ent at 18( 281) + 0 on 24;