neox
/
projet-vlsi
1
0
Fork 0
Code Issues Pull Requests Releases Activity

remplissage de exec_tb

This commit is contained in:
Adrien Bourmault 2022-01-20 18:09:43 +01:00
parent e16629bc54
commit c42e9315a5
No known key found for this signature in database
GPG Key ID: 6EB408FE0ACEC664
1 changed files with 341 additions and 118 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

453
exec_tb.vhdl
View File

@ -113,127 +113,350 @@ begin
ck <= not ck after 2 ns;
process
begin
-- decode interface synchro
dec2exe_empty <= '0';
-- decode interface operands
dec_op1 <= x"00000005"; --important
dec_op2 <= x"00000000"; --important
dec_exe_dest <= x"1";
dec_exe_wb <= '1';
dec_flag_wb <= '1';
-- decode to mem interface
dec_mem_data <= x"00000000";
dec_mem_dest <= x"2";
dec_pre_index <= '1'; -- important
dec_mem_lw <= '0';
dec_mem_lb <= '0';
dec_mem_sw <= '0';
dec_mem_sb <= '0';
--shifter command
dec_shift_lsl <= '0';
dec_shift_lsr <= '0';
dec_shift_asr <= '0';
dec_shift_ror <= '0';
dec_shift_rrx <= '0';
dec_shift_val <= "00000";
dec_cy <= '0';
-- Alu operand selection
dec_comp_op1 <= '0';
dec_comp_op2 <= '0';
dec_alu_cy <= '0';
-- alu command
dec_alu_cmd <= "01";
-- mem interface
mem_pop <= '0';
reset_n <= '1';
vdd <= '1';
vss <= '0';
-- add
ck <= '0';
wait for 2 ns;
wait for 10 ns;
-- addition de 2 et 1
dec_op1 <= x"00000002";
dec_op2 <= x"00000001";
dec_pre_index <= '0'; -- si 1 op1 si 0 op1 <OP> op2
--
dec_shift_lsl <= '0';
dec_shift_lsr <= '0';
dec_shift_asr <= '0';
dec_shift_ror <= '0';
dec_shift_rrx <= '0';
dec_shift_val <= "00000";
dec_cy <= '0';
---
dec_comp_op1 <= '0'; -- ~op1
dec_comp_op2 <= '0'; -- ~op2
dec_alu_cy <= '0'; -- carry complement a 2 les ops
dec_alu_cmd <= "00";-- commande "00" == add
reset_n <= '0';
ck <= '1';
wait for 2 ns;
wait for 10 ns;
assert exe_res = x"00000003" report "ERROR EXEC addition (2 et 1)" severity FAILURE;
ck <= '0';
wait for 2 ns;
-- soustraction de 3 et 1
dec_op1 <= x"00000002";
dec_op2 <= x"00000001";
dec_pre_index <= '0'; -- si 1 op1 si 0 op1 <OP> op2
--
dec_shift_lsl <= '0';
dec_shift_lsr <= '0';
dec_shift_asr <= '0';
dec_shift_ror <= '0';
dec_shift_rrx <= '0';
dec_shift_val <= "00000";
dec_cy <= '0';
---
dec_comp_op1 <= '0'; -- ~op1
dec_comp_op2 <= '1'; -- ~op2
dec_alu_cy <= '1'; -- carry complement a 2 les ops
dec_alu_cmd <= "00";-- commande "00" == add
wait for 10 ns;
assert exe_res = x"00000001" report "ERROR EXEC addition (2 et -1)" severity FAILURE;
dec_shift_lsl <= '0';
dec_shift_lsr <= '0';
dec_shift_asr <= '0';
dec_shift_ror <= '0';
dec_shift_rrx <= '0';
dec_shift_val <= "00000";
dec_alu_add <= '1';
dec_alu_and <= '0';
dec_alu_or <= '0';
dec_alu_xor <= '0';
dec_alu_cy <= '0';
dec_comp_op1 <= '0';
dec_comp_op2 <= '0';
dec_op1 <= x"0000000F";
dec_op2 <= x"0000000F";
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
ck <= '1';
wait;
-- add lsl
ck <= '0';
wait for 2 ns;
reset_n <= '0';
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
dec_shift_lsl <= '1';
dec_shift_lsr <= '0';
dec_shift_asr <= '0';
dec_shift_ror <= '0';
dec_shift_rrx <= '0';
dec_shift_val <= "00011"; --shift de 3
dec_alu_add <= '1';
dec_alu_and <= '0';
dec_alu_or <= '0';
dec_alu_xor <= '0';
dec_alu_cy <= '0';
dec_comp_op1 <= '0';
dec_comp_op2 <= '0';
dec_op1 <= x"0000000F";
dec_op2 <= x"000000E1";
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
ck <= '1';
wait;
-- and
ck <= '0';
wait for 2 ns;
reset_n <= '0';
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
dec_shift_lsl <= '0';
dec_shift_lsr <= '0';
dec_shift_asr <= '0';
dec_shift_ror <= '0';
dec_shift_rrx <= '0';
dec_shift_val <= "00000";
dec_alu_add <= '0';
dec_alu_and <= '1';
dec_alu_or <= '0';
dec_alu_xor <= '0';
dec_alu_cy <= '0';
dec_comp_op1 <= '0';
dec_comp_op2 <= '0';
dec_op1 <= x"01000001";
dec_op2 <= x"01000000";
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
ck <= '1';
wait;
-- and lsr
ck <= '0';
wait for 2 ns;
reset_n <= '0';
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
dec_shift_lsl <= '0';
dec_shift_lsr <= '1';
dec_shift_asr <= '0';
dec_shift_ror <= '0';
dec_shift_rrx <= '0';
dec_shift_val <= "11111";
dec_alu_add <= '0';
dec_alu_and <= '1';
dec_alu_or <= '0';
dec_alu_xor <= '0';
dec_alu_cy <= '0';
dec_comp_op1 <= '0';
dec_comp_op2 <= '0';
dec_op1 <= x"01000001";
dec_op2 <= x"FF000000";
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
ck <= '1';
wait;
-- mov
ck <= '0';
wait for 2 ns;
reset_n <= '0';
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
dec_shift_lsl <= '0';
dec_shift_lsr <= '0';
dec_shift_asr <= '0';
dec_shift_ror <= '0';
dec_shift_rrx <= '0';
dec_shift_val <= "00000";
dec_alu_add <= '0';
dec_alu_and <= '0';
dec_alu_or <= '1';
dec_alu_xor <= '0';
dec_alu_cy <= '0';
dec_comp_op1 <= '0';
dec_comp_op2 <= '0';
dec_zero_op1 <= '1';
dec_op1 <= x"FFFFFFFF";
dec_op2 <= x"12345678";
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
ck <= '1';
wait;
-- or asr
ck <= '0';
wait for 2 ns;
reset_n <= '0';
ck <= '1';
wait for 2 ns;
dec_shift_asr <= '1';
dec_shift_val <= "00001";
dec_op2 <= "1000" & x"0000002";
ck <= '0';
wait for 2 ns;
dec_shift_lsl <= '0';
dec_shift_lsr <= '0';
dec_shift_ror <= '0';
dec_shift_rrx <= '0';
dec_alu_add <= '0';
dec_alu_and <= '0';
dec_alu_or <= '1';
dec_alu_xor <= '0';
dec_alu_cy <= '0';
dec_comp_op1 <= '0';
dec_comp_op2 <= '0';
dec_op1 <= x"01000001";
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
ck <= '1';
wait;
-- or
ck <= '0';
wait for 2 ns;
reset_n <= '0';
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
dec_shift_lsl <= '0';
dec_shift_lsr <= '0';
dec_shift_asr <= '0';
dec_shift_ror <= '0';
dec_shift_rrx <= '0';
dec_shift_val <= "00000";
dec_alu_add <= '0';
dec_alu_and <= '0';
dec_alu_or <= '1';
dec_alu_xor <= '0';
dec_alu_cy <= '0';
dec_comp_op1 <= '0';
dec_comp_op2 <= '0';
dec_op1 <= x"01000001";
dec_op2 <= x"01000000";
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
ck <= '1';
wait;
-- xor
ck <= '0';
wait for 2 ns;
reset_n <= '0';
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
dec_shift_lsl <= '0';
dec_shift_lsr <= '0';
dec_shift_asr <= '0';
dec_shift_ror <= '0';
dec_shift_rrx <= '0';
dec_shift_val <= "00000";
dec_alu_add <= '0';
dec_alu_and <= '0';
dec_alu_or <= '0';
dec_alu_xor <= '1';
dec_alu_cy <= '0';
dec_comp_op1 <= '0';
dec_comp_op2 <= '0';
dec_op1 <= x"01000001";
dec_op2 <= x"01000000";
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
ck <= '1';
wait for 2 ns;
ck <= '0';
wait for 2 ns;
ck <= '1';
wait;
-- soustraction de 1 et 3
dec_op1 <= x"00000001";
dec_op2 <= x"00000003";
dec_pre_index <= '0'; -- si 1 op1 si 0 op1 <OP> op2
--
dec_shift_lsl <= '0';
dec_shift_lsr <= '0';
dec_shift_asr <= '0';
dec_shift_ror <= '0';
dec_shift_rrx <= '0';
dec_shift_val <= "00000";
dec_cy <= '0';
---
dec_comp_op1 <= '0'; -- ~op1
dec_comp_op2 <= '1'; -- ~op2
dec_alu_cy <= '1'; -- carry complement a 2 les ops
dec_alu_cmd <= "00";-- commande "00" == add
wait for 10 ns;
-- FFFFFFFE => -2
assert exe_res = x"FFFFFFFE" report "ERROR EXEC addition (1 et -3)" severity FAILURE;
-- soustraction de 1 et 8 (1 avec shift de 3)
dec_op1 <= x"00000001";
dec_op2 <= x"00000001";
dec_pre_index <= '0'; -- si 1 op1 si 0 op1 <OP> op2
--
dec_shift_lsl <= '1'; -- left shift
dec_shift_lsr <= '0';
dec_shift_asr <= '0';
dec_shift_ror <= '0';
dec_shift_rrx <= '0';
dec_shift_val <= "00011"; -- decalage de 3
dec_cy <= '0';
---
dec_comp_op1 <= '0'; -- op1
dec_comp_op2 <= '1'; -- ~op2
dec_alu_cy <= '1'; -- carry complement a 2 les ops
dec_alu_cmd <= "00";-- commande "00" == add
wait for 10 ns;
-- FFFFFFF9 => -7
assert exe_res = x"FFFFFFF9" report "ERROR EXEC addition (1 et -3)" severity FAILURE;
report "fin simu" severity FAILURE;
end process;
end Structurel;